Patent US5489059A successfully refreshed from Google Patents.
US5489059A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having an universal die size inner lead layout
Assignee: Adeia Semiconductor Technologies LLC
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Filing: 1995-02-10
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Granted: 1996-02-06
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Expires: 2015-02-10
Abstract
Abstract A substrate includes a non-conductive support layer and a plurality "n" of conductive leads disposed on the support layer. The leads are arranged in a generally radial pattern about a central point on the support layer, each of the leads having a width "w" and spaced a distance "d" from one another at their innermost ends, thereby forming a generally square opening of side dimension "s". The substrate accommodates semiconductor dies ranging in size from smaller than the opening, to approximately equal to that of the opening, to substantially larger than the opening, such as four times the size (linear dimension) of the opening. The die is bonded to the substrate. Other elements of a semiconductor device assembly are added to the resulting structure. Method and apparatus are disclosed.
Inventors
- 👤 Michael D. Rostoker
- 👤 Richard Brossart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:03
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W90/00; H10W90/701; H10W72/00; H10W72/071; H10W72/075; H10W72/50; H10W72/531; H10W72/5363; H10W72/5366; H10W72/541; H10W72/5449; H10W72/851; H10W72/874; H10W72/884; H10W74/00; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
185 words
A method of forming a semiconductor device assembly comprising: providing a substrate layer having a top surface and a bottom surface; providing upper conductive lead traces on the top surface of the substrate layer; arranging the upper conductive lead traces in a pattern directed to a central point on the substrate layer; extending the upper conductive lead traces towards, but not reaching, the central point, the upper conductive lead traces stopping short thereof and forming a generally square opening; providing lower conductive lead traces of the bottom surface of the substrate layer; providing a solder bump electrical termination on each lower conductive lead trace and electrically conductive thereto; providing conductive vias through the substrate layer such that they form electrical connections between the upper conductive lead traces and the lower conductive lead traces; mounting a semiconductor die atop the opening; and providing bond wires connecting the semiconductor die to the upper conductive lead traces; wherein the semiconductor die has a side dimension in a range of from smaller than the opening, to approximately equal to that of the opening, to substantially greater than the opening.
Claim 2
Independent Claim
185 words
A method of forming a semiconductor device assembly comprising: providing a substrate layer having a top surface and a bottom surface; providing upper conductive lead traces on the top surface of the substrate layer; arranging the upper conductive lead traces in a pattern directed to a central point on the substrate layer; extending the upper conductive lead traces towards, but not reaching, the central point, the upper conductive lead traces stopping short thereof and forming a generally square opening; providing lower conductive lead traces of the bottom surface of the substrate layer; providing a solder bump electrical termination on each lower conductive lead trace and electrically conductive thereto; providing conductive vias through the substrate layer such that they form electrical connections between the upper conductive lead traces and the lower conductive lead traces; mounting a semiconductor die atop the opening; and providing bond wires connecting the semiconductor die to the upper conductive lead traces; wherein the semiconductor die has a side dimension in a range of from smaller than the opening, to approximately equal to that of the opening, to substantially greater than the opening.
Claim 3
Dependent Claim
32 words
A method according to claim 1, wherein the semiconductor die has a side dimension in a range of from approximately equal to that of the opening to substantially greater than the opening.
Claim 4
Dependent Claim
17 words
A method according to claim 1, wherein the upper conductive lead traces extend substantially under the die.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |