US5172471A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of providing power to an integrated circuit
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1991-06-21
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Granted: 1992-12-22
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Expires: 2011-06-21
Abstract
Abstract A CMOS integrated circuit assembly for providing reduced power supply and ground inductances has a first conducting layer which is formed over an insulating layer formed on top of the integrated-circuit chip. The first conducting layer is connected to wire bond pads which are wirebonded to a package. This first conducting layer forms a single, low-inductance conductor for a VDD supply voltage and extends over a substantial area so that it has an inductance significantly less than the inductance of a conventional conductor. A second conducting layer is forms a low-inductance VSS conductor. Power can be selectively distributed through conductive layers of this to provide power supply isolation between selected circuits of the integrated circuit.
Inventors
- 👤 Chin C. Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:06
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W44/00; H10W44/501; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/5445; H10W72/547; H10W72/59; H10W72/931; H10W72/932; H10W72/981; H10W72/983; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
185 words
A method of providing power to an integrated circuit, comprising the steps of: forming an insulating layer on at least a portion of a semiconductor die, on which integrated circuit elements and a plurality of wirebonding pads are formed; forming a power-distribution conducting layer on said insulating layer, said conducting layer formed to have lateral dimensions significantly greater than the line width of a signal conductor formed on said semiconductor die, forming said conducting layer as a single conducting region, which is connected to one or more wirebonding pads on said semiconductor die, which extends over a substantial area of the semiconductor die, and which has an inductance significantly less than the inductance of one of said signal conductors, said conducting layer providing a connection for a first voltage reference source to a first selected region of said integrated circuit; mounting the semiconductor die in a wirebond package, which has external connection pins mounted thereto; and electrically connecting the external connection pins of said wirebonding package to selected ones of said wirebonding pads by connecting including bonding wires to wirebond pads on said semiconductor die.
Claim 2
Independent Claim
185 words
A method of providing power to an integrated circuit, comprising the steps of: forming an insulating layer on at least a portion of a semiconductor die, on which integrated circuit elements and a plurality of wirebonding pads are formed; forming a power-distribution conducting layer on said insulating layer, said conducting layer formed to have lateral dimensions significantly greater than the line width of a signal conductor formed on said semiconductor die, forming said conducting layer as a single conducting region, which is connected to one or more wirebonding pads on said semiconductor die, which extends over a substantial area of the semiconductor die, and which has an inductance significantly less than the inductance of one of said signal conductors, said conducting layer providing a connection for a first voltage reference source to a first selected region of said integrated circuit; mounting the semiconductor die in a wirebond package, which has external connection pins mounted thereto; and electrically connecting the external connection pins of said wirebonding package to selected ones of said wirebonding pads by connecting including bonding wires to wirebond pads on said semiconductor die.
Claim 3
Dependent Claim
24 words
The method of claim 1 including the step of connecting the conducting layer with conductive strips to respective wirebonding pads on the semiconductor die.
Claim 4
Dependent Claim
26 words
The method of claim 1 including the step of connecting with conductive vias the conducting layer to points within the circuits formed on said semiconductor die.
Claim 5
Independent Claim
276 words
A method of providing power to an integrated circuit, comprising the steps of: forming an insulating layer on at least a portion of a semiconductor die, on which integrated circuit elements and a plurality of wirebonding pads are formed; forming a first conducting layer on said insulating layer, said first conducting layer formed to have lateral dimensions significantly greater than the line width of a signal conductor formed on said semiconductor die, forming said first conducting layer as a single conducting region, which is connected to one or more wirebonding pads on said semiconductor die, which extends over a substantial area of the semiconductor die, and which has an inductance significantly less than the inductance of one of said signal conductors, said first conducting layer providing a connection for a first voltage reference source to a first selected region of said integrated circuit; forming a second conducting layer on said insulating layer, said second conducting layer having lateral dimensions significantly greater than the line width of the signal conductors formed on said semiconductor die, forming said second conducting layer as a single conducting region which extends over a substantial area of said semiconductor substrate and which has an inductance significantly less than the inductance of an interconnection conductor, said first conducting layer providing a connection for a second voltage reference source to a second selected region of said integrated circuit; mounting the semiconductor die in a wirebond package, which has external connection pins mounted thereto; and electrically connecting the external connection pins of said wirebonding package to selected ones of said wirebonding pads by connecting means including bonding wires to wirebond pads on said semiconductor die.
Claim 6
Independent Claim
276 words
A method of providing power to an integrated circuit, comprising the steps of: forming an insulating layer on at least a portion of a semiconductor die, on which integrated circuit elements and a plurality of wirebonding pads are formed; forming a first conducting layer on said insulating layer, said first conducting layer formed to have lateral dimensions significantly greater than the line width of a signal conductor formed on said semiconductor die, forming said first conducting layer as a single conducting region, which is connected to one or more wirebonding pads on said semiconductor die, which extends over a substantial area of the semiconductor die, and which has an inductance significantly less than the inductance of one of said signal conductors, said first conducting layer providing a connection for a first voltage reference source to a first selected region of said integrated circuit; forming a second conducting layer on said insulating layer, said second conducting layer having lateral dimensions significantly greater than the line width of the signal conductors formed on said semiconductor die, forming said second conducting layer as a single conducting region which extends over a substantial area of said semiconductor substrate and which has an inductance significantly less than the inductance of an interconnection conductor, said first conducting layer providing a connection for a second voltage reference source to a second selected region of said integrated circuit; mounting the semiconductor die in a wirebond package, which has external connection pins mounted thereto; and electrically connecting the external connection pins of said wirebonding package to selected ones of said wirebonding pads by connecting means including bonding wires to wirebond pads on said semiconductor die.
Claim 7
Dependent Claim
28 words
The method of claim 4 including the step of connecting the first and the second conducting layers with conductive strips to respective wirebonding pads on the semiconductor die.
Claim 8
Dependent Claim
30 words
The method of claim 4 including the step of connecting with conductive vias the first and the second conducting layers to points within the circuits formed on said semiconductor die.
References Cited (Backward Citations)
US3408542A
Cited
US3535530A
Cited
US3786375A
Cited
US3745487A
Cited
US4023198A
Cited
US4128802A
Cited
US4117508A
Cited
US4514587A
Cited
US4926545A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-22 | 1996-06-22 | 1996-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-22 | 2000-06-22 | 2000-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-22 | 2004-06-22 | 2004-12-22 | $7700.00 | Window Closed / Lapsed |