Cache including decoupling register circuits

Claim 2

A cache memory apparatus comprising: a random access memory; a host port; a system port; a memory write register for buffering first data received from said host port and selectively providing the first data to one of said random access memory, said system port, and said random access memory and said system port, said memory write register being coupled between said host port and said random access memory and between said host port and said system port; and a write back register for holding second data received from said random access memory and selectively providing the second data to said system port, said write back register being coupled between said random access memory and said system port; wherein the buffering and selective providing of the first data to said random access memory and the holding and selective providing of the second data to said system port allows memory accesses at said host port to be decoupled from memory accesses at said system port.

Claim 3

The cache memory apparatus as recited in claim 1 further comprising a read hold register coupled between said random access memory and said host port for buffering and providing burst read data from said random access memory to said host port.

Claim 4

The cache memory apparatus as recited in claim 1 further comprising a bypass path coupled between said host port and said system port for directly allowing passage of data between said host port and said system port.

Claim 5

The cache memory apparatus as recited in claim 1 wherein said random access memory includes storage for a plurality of parity bits.

Claim 6

The cache memory apparatus as recited in claim 1 wherein said random access memory is organized in a plurality of lines wherein each of said lines comprises a plurality of word storage locations, and wherein each of said word storage locations is selectively writable.

Claim 7

The cache memory apparatus as recited in claim 1 wherein said random access memory is written using a read-modify-write operation.

Claim 8

The cache memory apparatus as recited in claim 1 wherein said random access memory is single ported.

Claim 9

The cache memory apparatus as recited in claim 7 wherein said random access memory is accessed with a wider bandwidth than said host port and said system port.

Claim 10

An apparatus as in claim 1, further comprising a memory update register for holding fetched data and providing the fetched data to said random access memory, said memory update register being coupled between said random access memory and said system port, wherein the holding and selective providing of the second data and the holding of the fetched data allows write back and fetch operations at said system port to be decoupled from said random access memory.

Claim 11

The cache memory apparatus as recited in claim 9 further comprising means for identifying ones of the fetched data held in said memory update register as not corresponding to ones of the second data held in said write back register for write back to said system port, said identifying means being selective for the ones of the fetched data to be provided from said memory update register to said random access memory.

Claim 12

The cache memory apparatus as recited in claim 9 wherein said memory update register can store a plurality of words of the fetched data.

Claim 13

The cache memory apparatus as recited in claim 11 further comprising means for masking the providing of selected ones of said words of the fetched data to said random access memory.

Claim 14

A cache memory apparatus comprising: a random access memory; a host port; a system port; a memory write register coupled to said random access memory, to said host port, and to said system port for buffering and selectively providing input data received from said host port to one of said random access memory, said system port, and said random access memory and said system port; and a write back register coupled to said system port and to said random access memory for holding output data received from said random access memory and selectively providing said output data to said system port; wherein the input data is provided to said random access memory from said memory write register at the same time that the output data is provided by said write back register to said system port, the buffering and selective providing of the input data to said random access memory and the holding and selective providing of the output data to said system port allowing memory accesses at said host port to be decoupled from memory accesses at said system port.

Claim 15

A cache memory apparatus comprising: a random access memory; a host port; a system port; a memory write register coupled to said random access memory, to said host port, and to said system port for buffering and selectively providing input data received from said host port to one of said random access memory, said system port, and said random access memory and said system port; and a write back register coupled to said system port and to said random access memory for holding output data received from said random access memory and selectively providing said output data to said system port; wherein the input data is provided to said random access memory from said memory write register at the same time that the output data is provided by said write back register to said system port, the buffering and selective providing of the input data to said random access memory and the holding and selective providing of the output data to said system port allowing memory accesses at said host port to be decoupled from memory accesses at said system port.

Claim 16

The cache memory apparatus as recited in claim 13 further comprising: a miss address register coupled to said host port and to said random access memory for storing a cache miss address signal corresponding to a word of the output data to be received from said random access memory into said write back register; and a hit address register coupled to said host port and to said random access memory for storing a cache hit address signal selective for a word stored in said random access memory.

Claim 17

The cache memory apparatus as recited in claim 14 further comprising a counter coupled to said miss address register.

Claim 18

The cache memory apparatus as recited in claim 15 wherein said counter increments from an address associated with a first line of data to an address associated with a subsequent line of data.

Claim 19

A cache memory apparatus comprising: a random access memory; a host port; a system port; a memory write register for buffering and selectively writing first input data to said random access memory, said memory write register being coupled between said host port and said random access memory; a write back register for holding and selectively furnishing first output data to said system port, said write back register being coupled between said random access memory and said system port, the first input data being provided to said random access memory from said memory write register at the same time that the first output data is provided by said write back register to said system port, the selective writing of the first input data to said random access memory and the selective furnishing of the first output data to said system port allowing memory accesses at said host port to be decoupled from memory accesses at said system port; a memory update register for holding and selectively providing second input data to said random access memory, said memory update register being coupled between said random access memory and said system port, wherein the holding and selective furnishing of the first output data and the holding and selective providing of the second input data allows write back and memory update operations at said system port to be decoupled from said random access memory; and, a read hold register coupled between said random access memory and said host port for providing second output data from said random access memory to said host port, the second input data being provided to said random access memory from said memory update register at the same time that the second output data is provided by said read hold register to said host port.

Claim 20

A cache memory apparatus comprising: a random access memory; a host port; a system port; a memory write register for buffering and selectively writing first input data to said random access memory, said memory write register being coupled between said host port and said random access memory; a write back register for holding and selectively furnishing first output data to said system port, said write back register being coupled between said random access memory and said system port, the first input data being provided to said random access memory from said memory write register at the same time that the first output data is provided by said write back register to said system port, the selective writing of the first input data to said random access memory and the selective furnishing of the first output data to said system port allowing memory accesses at said host port to be decoupled from memory accesses at said system port; a memory update register for holding and selectively providing second input data to said random access memory, said memory update register being coupled between said random access memory and said system port, wherein the holding and selective furnishing of the first output data and the holding and selective providing of the second input data allows write back and memory update operations at said system port to be decoupled from said random access memory; and, a read hold register coupled between said random access memory and said host port for providing second output data from said random access memory to said host port, the second input data being provided to said random access memory from said memory update register at the same time that the second output data is provided by said read hold register to said host port.

Claim 21

An apparatus as recited in claim 17 further comprising a bypass path coupled between said host port and said system port for directly allowing passage of data between said host port and said system port.

Claim 22

The cache memory apparatus as recited in claim 17 wherein said memory update register can store a plurality of words of the second input data.

Claim 23

An apparatus as recited in claim 17, wherein the first input data comprises memory write data, the second input data comprises system fetch data, the first output data comprises system write back data, and the second output comprises burst read data.

Claim 24

The cache memory apparatus as recited in claim 20 further comprising means for masking writing of selected words of the system fetch data into said random access memory.

Claim 25

A cache memory apparatus comprising: a random access memory; a host port; a system port; a bypass path coupled between said host port and said system port for directly passing data between said host port and said system port; a memory write register for buffering and selectively providing memory write data to one of said random access memory, said system port via said bypass path, and said random access memory and said system port via said bypass path, said memory write register being coupled to said bypass path and between said host port and said random access memory; a write back register for holding and selectively furnishing write back data to said system port, said write back register being coupled between said random access memory and said system port, said write back register allowing the write back data to be furnished to said system port at the same time that said memory write register provides the memory write data to said random access memory; a memory update register for holding and selectively providing system fetch data to said random access memory, said memory update register being coupled between said random access memory and said system port, wherein the holding and selective furnishing of the write back data and the holding and selectively providing of the system fetch data allows write back and memory update operations at said system port to be decoupled from said random access memory; and a read hold register coupled between said random access memory and said host port for buffering and providing burst read data from said random access memory to said host port, said read hold register allowing the burst read data to be provided to said host port at the same time that said memory update register provides the system fetch data to said random access memory.

Claim 26

A cache memory apparatus comprising: a random access memory; a host port; a system port; a bypass path coupled between said host port and said system port for directly passing data between said host port and said system port; a memory write register for buffering and selectively providing memory write data to one of said random access memory, said system port via said bypass path, and said random access memory and said system port via said bypass path, said memory write register being coupled to said bypass path and between said host port and said random access memory; a write back register for holding and selectively furnishing write back data to said system port, said write back register being coupled between said random access memory and said system port, said write back register allowing the write back data to be furnished to said system port at the same time that said memory write register provides the memory write data to said random access memory; a memory update register for holding and selectively providing system fetch data to said random access memory, said memory update register being coupled between said random access memory and said system port, wherein the holding and selective furnishing of the write back data and the holding and selectively providing of the system fetch data allows write back and memory update operations at said system port to be decoupled from said random access memory; and a read hold register coupled between said random access memory and said host port for buffering and providing burst read data from said random access memory to said host port, said read hold register allowing the burst read data to be provided to said host port at the same time that said memory update register provides the system fetch data to said random access memory.

Claim 27

The cache memory apparatus as recited in claim 22 wherein said memory update register can store a plurality of words of the system fetch data.

Claim 28

The cache memory apparatus as recited in claim 22 further comprising means for masking writing of selected words of the system fetch data into said random access memory.

Claim 29

The cache memory apparatus as recited in claim 22 further comprising: a miss address register coupled to said host port and to said random access memory for storing a cache miss address signal, the cache miss address signal being selective for words of the fetch data to be received into said memory update register and corresponding to words of the write back data to be held in said write back register and replaced in said random access memory by the words of fetch data; and a hit address register coupled to said host port and to said random access memory for storing a cache hit address signal selective for a word stored in said random access memory.

Claim 30

The cache memory apparatus as recited in claim 22 further comprising means for identifying ones of the fetched data held in said memory update register as not corresponding to ones of the write back data held in said write back register for write back to said system port, said identifying means being selective for the ones of the fetched data to be provided from said memory update register to said random access memory.