Method and apparatus for field testing field programmable logic arrays

Claim 1

A self-testable, field programmable gate array having a plurality of individual gates, each of said gates comprising a non-volatile floating gate field effect transistor logically in series with a volatile field effect transistor, said gate array comprising means for selectively changing the state of selected non-volatile floating gate field effect transistors to program the gate array; said gate array being programmably divisible into four logical areas, said areas comprising: a. a first logical area comprising a programmable logic gate array sea of gates having an AND-plane and an OR-plane; b. a second logical area comprising pseudo random pattern generator register means to apply a pseudo random set of test patterns to the programmable logic gate array sea of gates; c. a third logical area comprising multiple input signature register means to capture the output of the programmable logic gate array sea of gates with respect to test patterns generated by the pseudo random pattern generator means; and d. a fourth logical area comprising comparator means to compare the input pseudo random set of test patterns received by the sea of gates to the sea of gates output received by the multiple input signature register means from the sea of gates.

Claim 3

A method of field programming a self testable, field programmable logic array having a programmable logic gate array sea of gates having an AND-plane and an OR-plane, each gate comprising a non-volatile floating gate field effect transistor in series with a field effect transistor, said method comprising the steps of: a. setting said non-volatile gates to zero; b. configuring the logic array into (1) pseudo random pattern generator, (2) multiple input signature register, (3) signature comparator, and (4) AND-plane, OR-plane logic array areas; c. applying a pseudo random set of test patterns from the pseudo random pattern generator to the programmable logic gate array AND-plane, OR-plane sea of gates; d. capturing in the multiple input signature register means the output of the programmable logic gate array sea of gates with respect to test patterns generated by the pseudo random pattern generator means; e. comparing, in the comparator means, i. the input pseudo random set of test patterns received by the sea of gates to ii. the sea of gates output received from the sea of gates by the multiple input signature register means; and f. thereafter selectively setting selected ones of said non-volatile gates to zero or one as appropriate.

Claim 4

A method of field programming a self testable, field programmable logic array having a programmable logic gate array sea of gates having an AND-plane and an OR-plane, each gate comprising a non-volatile floating gate field effect transistor in series with a field effect transistor, said method comprising the steps of: a. setting said non-volatile gates to zero; b. configuring the logic array into (1) pseudo random pattern generator, (2) multiple input signature register, (3) signature comparator, and (4) AND-plane, OR-plane logic array areas; c. applying a pseudo random set of test patterns from the pseudo random pattern generator to the programmable logic gate array AND-plane, OR-plane sea of gates; d. capturing in the multiple input signature register means the output of the programmable logic gate array sea of gates with respect to test patterns generated by the pseudo random pattern generator means; e. comparing, in the comparator means, i. the input pseudo random set of test patterns received by the sea of gates to ii. the sea of gates output received from the sea of gates by the multiple input signature register means; and f. thereafter selectively setting selected ones of said non-volatile gates to zero or one as appropriate.