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US5487218A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making printed circuit boards with selectivity filled plated through holes

Assignee: Adeia Semiconductor Technologies LLC
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Filing: 1994-11-21
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Granted: 1996-01-30
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Expires: 2014-11-21
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Abstract

Abstract Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Inventors

  • 👤 Anilkumar C. Bhatt
  • 👤 Roy H. Magnuson
  • 👤 Voya R. Markovich
  • 👤 Konstantinos I. Papathomas
  • 👤 Douglas O. Powell

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 10:58
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/0094; H05K3/40; H05K1/00; H05K1/02; H05K1/11; H05K1/111; H05K1/112; H05K3/46; H05K3/4602; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H05K2201/00; H05K2201/09; H05K2201/09145; H05K2201/092; H05K2201/09209; H05K2201/09372; H05K2201/09472; H05K2201/095; H05K2201/09509; H05K2201/09536; H05K2201/0959; H05K2201/096; H05K2201/09818; H05K2201/09845; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10734; H05K2203/00; H05K2203/01; H05K2203/0191; H05K2203/02; H05K2203/0278; H05K3/0011; H05K3/0017; H05K3/0023; H05K3/42; H05K3/429; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/49155; Y10T29/49165

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 359 words
A method of preparing a printed circuit board having a film redistribution layer and selective filled plated through holes comprising the steps of: a. drilling a pattern of holes through a subcomposite for plated through holes, and drilling a sheet of polyimide with the same plated through hole pattern; b. be seeding the drilled subcomposite with a palladium/tin colloidal suspension whereby to make the exposed surfaces catalytic for electroless Cu plating; c. electrolessly plating copper over the exposed surfaces of the subcomposite and in the plated through hole barrels to a thickness of about 0.001 to 0.0012 inch; d. placing a sheet of foil coated with plated through hole filler composition atop the sub-composite to form a stack; e. laminating the stack to cause the coating composition to soften and flow into the plated through holes and thereafter cure; f. drilling the subcomposite with the pattern of plated through holes that are to remain unfilled, deburring, and chemical hole cleaning the unfilled plated through hole barrels for plating; g. seeding the subcomposite with a palladium/tin colloidal suspension, and electrolessly copper plating the seeded subcomposite with an additional 0.0002 to 0.0003 inch of copper; h. applying a layer of photoresist to the subcomposite, and exposing and developing the layer of photoresist to define a desired pattern of surface circuitization; i. etching the exposed surface of the subcomposite to form a desired circuit pattern; j. stripping the photoresist; k. applying a dry film photoimagable, dielectric polymer, to one or both surfaces of the subcomposite; l. exposing the photoimagable dielectric with the pattern of the desired vias between the subcomposite circuitry and the circuitry to be formed on the top surface of the dielectric; m. developing the pattern of via openings, and thereafter processing the dielectric to further cure the dielectric; n. seeding the dielectric is seeded with colloidal palladium/tin; o. laminating a subsequent dry film photoresist layer thereto, over the palladium/tin seed layer; imaging the photoresist with the image of the circuitization to be formed, and developing the imaged photoresist; p. plating the subcomposite with copper to form a film redistribution layer thereon; q. stripping the photomask from the circuitized composite.
Claim 2
Independent Claim 359 words
A method of preparing a printed circuit board having a film redistribution layer and selective filled plated through holes comprising the steps of: a. drilling a pattern of holes through a subcomposite for plated through holes, and drilling a sheet of polyimide with the same plated through hole pattern; b. be seeding the drilled subcomposite with a palladium/tin colloidal suspension whereby to make the exposed surfaces catalytic for electroless Cu plating; c. electrolessly plating copper over the exposed surfaces of the subcomposite and in the plated through hole barrels to a thickness of about 0.001 to 0.0012 inch; d. placing a sheet of foil coated with plated through hole filler composition atop the sub-composite to form a stack; e. laminating the stack to cause the coating composition to soften and flow into the plated through holes and thereafter cure; f. drilling the subcomposite with the pattern of plated through holes that are to remain unfilled, deburring, and chemical hole cleaning the unfilled plated through hole barrels for plating; g. seeding the subcomposite with a palladium/tin colloidal suspension, and electrolessly copper plating the seeded subcomposite with an additional 0.0002 to 0.0003 inch of copper; h. applying a layer of photoresist to the subcomposite, and exposing and developing the layer of photoresist to define a desired pattern of surface circuitization; i. etching the exposed surface of the subcomposite to form a desired circuit pattern; j. stripping the photoresist; k. applying a dry film photoimagable, dielectric polymer, to one or both surfaces of the subcomposite; l. exposing the photoimagable dielectric with the pattern of the desired vias between the subcomposite circuitry and the circuitry to be formed on the top surface of the dielectric; m. developing the pattern of via openings, and thereafter processing the dielectric to further cure the dielectric; n. seeding the dielectric is seeded with colloidal palladium/tin; o. laminating a subsequent dry film photoresist layer thereto, over the palladium/tin seed layer; imaging the photoresist with the image of the circuitization to be formed, and developing the imaged photoresist; p. plating the subcomposite with copper to form a film redistribution layer thereon; q. stripping the photomask from the circuitized composite.
Claim 3
Independent Claim 446 words
A method of preparing a printed circuit board having a film redistribution layer and selective filled plated through holes comprising the steps of: a. laminating a printed circuit board subcomposite with 0.5 ounce/square foot Cu foil on both sides thereof; b. thinning the copper foil to about 0.00025 inch; c. drilling a pattern of holes through the subcomposite for plated through holes, and drilling a sheet of polyimide with the same plated through hole pattern; d. seeding the drilled subcomposite with a palladium/tin colloidal suspension whereby to make the exposed surfaces catalytic for electroless Cu plating; e. electrolessly plating copper over the exposed surfaces of the subcomposite and in the plated through hole barrels to a thickness of about 0.001 to 0.0012 inch; f. positioning the drilled polyimide sheet on the sub-composite aligned with the plated through holes; g. placing a sheet of foil coated with plated through hole filler composition atop the sub-composite to form a stack; h. laminating the stack to cause the coating composition to soften and flow through the holes in the drilled polyimide into the plated through holes and thereafter cure; i. abrading the surface thereof to remove nubs of the fill material from the tops of the filled plated through holes, and remove fill residues on the surface of the copper foil from bleed between the mask and the sub-composite; j. drilling the subcomposite with the pattern of plated through holes that are to remain unfilled, deburring, and chemical hole cleaning the unfilled plated through hole barrels for plating; k. seeding the subcomposite with a palladium/tin colloidal suspension, and electrolessly copper plating the seeded subcomposite with an additional 0.0002 to 0.0003 inch of copper; l. applying a layer of :photoresist to the subcomposite, and exposing and developing the layer of photoresist to define a desired pattern of surface circuitization; m. etching the exposed surface of the subcomposite to form a desired circuit pattern; n. stripping the photoresist; o. applying a dry film photoimagable, dielectric polymer, to one or both surfaces of the subcomposite; p. exposing the photoimagable dielectric with the pattern of the desired vias between the subcomposite circuitry and the circuitry to be formed on the top surface of the dielectric; q. developing the pattern of via openings, and thereafter processing the dielectric to further cure the dielectric; r. seeding the dielectric with a colloidal palladium/tin suspension; s. laminating a subsequent dry film photoresist layer thereto, over the palladium/tin seed layer; imaging the photoresist with the image of the circuitization to be formed, and developing the imaged photoresist; t. plating the subcomposite with copper to form a film redistribution layer thereon; u. stripping the photomask from the circuitized composite.
Claim 4
Independent Claim 446 words
A method of preparing a printed circuit board having a film redistribution layer and selective filled plated through holes comprising the steps of: a. laminating a printed circuit board subcomposite with 0.5 ounce/square foot Cu foil on both sides thereof; b. thinning the copper foil to about 0.00025 inch; c. drilling a pattern of holes through the subcomposite for plated through holes, and drilling a sheet of polyimide with the same plated through hole pattern; d. seeding the drilled subcomposite with a palladium/tin colloidal suspension whereby to make the exposed surfaces catalytic for electroless Cu plating; e. electrolessly plating copper over the exposed surfaces of the subcomposite and in the plated through hole barrels to a thickness of about 0.001 to 0.0012 inch; f. positioning the drilled polyimide sheet on the sub-composite aligned with the plated through holes; g. placing a sheet of foil coated with plated through hole filler composition atop the sub-composite to form a stack; h. laminating the stack to cause the coating composition to soften and flow through the holes in the drilled polyimide into the plated through holes and thereafter cure; i. abrading the surface thereof to remove nubs of the fill material from the tops of the filled plated through holes, and remove fill residues on the surface of the copper foil from bleed between the mask and the sub-composite; j. drilling the subcomposite with the pattern of plated through holes that are to remain unfilled, deburring, and chemical hole cleaning the unfilled plated through hole barrels for plating; k. seeding the subcomposite with a palladium/tin colloidal suspension, and electrolessly copper plating the seeded subcomposite with an additional 0.0002 to 0.0003 inch of copper; l. applying a layer of :photoresist to the subcomposite, and exposing and developing the layer of photoresist to define a desired pattern of surface circuitization; m. etching the exposed surface of the subcomposite to form a desired circuit pattern; n. stripping the photoresist; o. applying a dry film photoimagable, dielectric polymer, to one or both surfaces of the subcomposite; p. exposing the photoimagable dielectric with the pattern of the desired vias between the subcomposite circuitry and the circuitry to be formed on the top surface of the dielectric; q. developing the pattern of via openings, and thereafter processing the dielectric to further cure the dielectric; r. seeding the dielectric with a colloidal palladium/tin suspension; s. laminating a subsequent dry film photoresist layer thereto, over the palladium/tin seed layer; imaging the photoresist with the image of the circuitization to be formed, and developing the imaged photoresist; t. plating the subcomposite with copper to form a film redistribution layer thereon; u. stripping the photomask from the circuitized composite.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-01-29 1999-07-31 2000-01-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-01-29 2003-07-31 2004-01-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-01-29 2007-07-31 2008-01-30 $7700.00 Window Closed / Lapsed

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