Generation of a clock frequency in a smart card interface

Claim 1

A circuit arrangement for generating a clock signal of a predetermined frequency for a smart card interface which couples data from a smart card to a device, the data being transferred at a predetermined data rate, the arrangement comprising means for deriving the smart card interface clock signal from a smart card clock signal coupled to the arrangement, such that the frequency of the smart card interface clock signal and the data rate are of a predetermined ratio; wherein said deriving means comprises gating means for outputting selective pulses of the smart card clock signal to serve as said smart card interface clock signal; said deriving means of the arrangement comprises a phase locked loop and at least one counter coupled to an input thereof, said one counter dividing a frequency of said smart card clock signal to output an input signal to said phase locked loop, the phase locked loop including said gating means, said one counter having a predetermined coefficient to provide said predetermined ratio; said phase locked loop is a digitally operated phase locked loop responsive to a drive clock signal, said arrangement further comprising a second counter for dividing the frequency of said smart card clock signal to output said drive clock signal; and said phase locked loop has a locking range inversely proportional to a frequency division ratio of said second counter, the frequency division ratio of said one counter placing a frequency of said input signal to said phase locked loop within said locking range.