Patent US5487025A successfully refreshed from Google Patents.
US5487025A
Expired / Lapsed
US
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Carry chain adder using regenerative push-pull differential logic
Assignee: Intergraph Corp
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Filing: 1993-11-15
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Granted: 1996-01-23
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Expires: 2013-11-15
Abstract
Abstract A carry indicating circuit selectively generates a carry-in signal indicating whether the addition of a first plurality of bits results in a carry. A first carry chain circuit selectively generates a first carry-out signal indicating whether the addition of a second plurality of bits together with a carry from the addition of the first plurality of bits results in a carry, and a second carry chain circuit selectively generates a second carry-out signal indicating whether the addition of the second plurality of bits without a carry from the addition of the first plurality of bits results in a carry. Selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, selects either the first carry-out signal or the second carry-out signal in response to the carry-in signal. The first and second carry chain circuits and/or the selection circuitry each includes a first transistor connected to a second transistor so that the first and second transistors may be initially biased in a nonconducting state when a first node is at a first voltage potential and a second node is at a second voltage potential, the first voltage potential being different from the second voltage potential. Altering circuitry is provided for altering the voltage potential at the first and second nodes for causing the first and second transistors to be in a conducting state and for accelerating the voltage at the first and second nodes to final voltage potentials.
Inventors
- 👤 Hamid Partovi
- 👤 Donald A. Draper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:57
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503; G06F7/505; G06F7/506; G06F7/507; H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01742; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3872
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
297 words
A circuit for adding binary numbers comprising: a carry indicating circuit for generating a carry-in signal indicating whether the addition of a first plurality of bits of the binary numbers to be added results in a carry; a first carry chain circuit connected to the carry indicating circuit for generating a first carry-out signal indicating whether the addition of a second plurality of bits of the binary numbers to be added together with a carry from the addition of the first plurality of bits of the binary numbers to be added results in a carry; a second carry chain circuit connected to the carry indicating circuit for generating a second carry-out signal indicating whether the addition of the second plurality of bits of the binary numbers to be added without a carry from the addition of the first plurality of bits of the binary numbers to be added results in a carry; and wherein the first and second carry chain circuits each include: a first transistor connected to a second transistor so that the first and second transistors may be initially biased in a nonconducting state when a first node is at a first voltage potential and a second node is at a second voltage potential, the first voltage potential being different from the second voltage potential; and altering means for altering the voltage potential at the first and second nodes and for causing the first and second transistors to be in a conducting state and for accelerating the voltage change at the first and second nodes to final voltage potentials; and selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, for selecting either the first carry-out signal or the second carry-out signal in response to the carry-in signal.
Claim 2
Dependent Claim
297 words
A circuit for adding binary numbers comprising: a carry indicating circuit for generating a carry-in signal indicating whether the addition of a first plurality of bits of the binary numbers to be added results in a carry; a first carry chain circuit connected to the carry indicating circuit for generating a first carry-out signal indicating whether the addition of a second plurality of bits of the binary numbers to be added together with a carry from the addition of the first plurality of bits of the binary numbers to be added results in a carry; a second carry chain circuit connected to the carry indicating circuit for generating a second carry-out signal indicating whether the addition of the second plurality of bits of the binary numbers to be added without a carry from the addition of the first plurality of bits of the binary numbers to be added results in a carry; and wherein the first and second carry chain circuits each include: a first transistor connected to a second transistor so that the first and second transistors may be initially biased in a nonconducting state when a first node is at a first voltage potential and a second node is at a second voltage potential, the first voltage potential being different from the second voltage potential; and altering means for altering the voltage potential at the first and second nodes and for causing the first and second transistors to be in a conducting state and for accelerating the voltage change at the first and second nodes to final voltage potentials; and selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, for selecting either the first carry-out signal or the second carry-out signal in response to the carry-in signal.
Claim 3
Dependent Claim
296 words
A circuit for adding binary numbers comprising: a carry indicating circuit for generating a carry-in signal indicating whether the addition of a first plurality of bits of the binary numbers to be added results in a carry; a first carry chain circuit connected to the carry indicating circuit for generating a first carry-out signal indicating whether the addition of a second plurality of bits of the binary numbers to be added together with a carry from the addition of the first plurality of bits of the binary numbers to be added results in a carry; a second carry chain circuit connected to the carry indicating circuit for generating a second carry-out signal indicating whether the addition of the second plurality of bits of the binary numbers to be added without a carry from the addition of the first plurality of bits of the binary numbers to be added results in a carry; and selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, for selecting either the first carry-out signal or the second carry-out signal in response to the carry-in signal; wherein the selection circuitry includes: a first transistor connected to a second transistor so that the first and second transistors may be initially biased in a nonconducting state when a first node is at a first voltage potential and a second node is at a second voltage potential, the first voltage potential being different from the second voltage potential; and altering means for altering the voltage potential at the first and second nodes in response to the carry-in signal for causing the first and second transistors to be in a conducting state and for accelerating the voltage change at the first and second nodes to final voltage potentials.
Claim 4
Dependent Claim
296 words
A circuit for adding binary numbers comprising: a carry indicating circuit for generating a carry-in signal indicating whether the addition of a first plurality of bits of the binary numbers to be added results in a carry; a first carry chain circuit connected to the carry indicating circuit for generating a first carry-out signal indicating whether the addition of a second plurality of bits of the binary numbers to be added together with a carry from the addition of the first plurality of bits of the binary numbers to be added results in a carry; a second carry chain circuit connected to the carry indicating circuit for generating a second carry-out signal indicating whether the addition of the second plurality of bits of the binary numbers to be added without a carry from the addition of the first plurality of bits of the binary numbers to be added results in a carry; and selection circuitry, coupled to the carry indicating circuit and to the first and second carry chain circuits, for selecting either the first carry-out signal or the second carry-out signal in response to the carry-in signal; wherein the selection circuitry includes: a first transistor connected to a second transistor so that the first and second transistors may be initially biased in a nonconducting state when a first node is at a first voltage potential and a second node is at a second voltage potential, the first voltage potential being different from the second voltage potential; and altering means for altering the voltage potential at the first and second nodes in response to the carry-in signal for causing the first and second transistors to be in a conducting state and for accelerating the voltage change at the first and second nodes to final voltage potentials.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-22 | 1999-07-24 | 2000-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-22 | 2003-07-24 | 2004-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-22 | 2007-07-24 | 2008-01-23 | $7700.00 | Window Closed / Lapsed |