US5270955A
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Method of detecting arithmetic or logical computation result
Assignee: Texas Instruments Inc
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Filing: 1992-07-31
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Granted: 1993-12-14
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Expires: 2012-07-31
Abstract
Abstract An arithmetic or logical computation result detection circuit is described. The circuit has a set of one-bit-zero cells which receive a first operand, A, a second operand, B, and a C in , and generates a set of one-bit-zero signals, Z. A combinatorial circuit receives the set of one-bit-zero signals and provides a selected output which is a known function of the one-bit-zero signals. In a preferred embodiment, the combinatorial circuit is a logical AND function which detects a condition when all the one-bit-zero signals are positively asserted. In various embodiments of the preferred invention the one-bit-zero signals may be operable to detect an arithmetic zero condition for operations of addition, subtraction, or a logic operation. Other devices, systems and methods are also disclosed.
Inventors
- 👤 Patrick W. Bosshart
- 👤 Sanjive Agarwala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:53
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/02; G06F9/00; G06F9/06; G06F9/30; G06F9/30094; G06F7/499; G06F7/49905
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
206 words
A method of detecting if the nth bit of the result of an arithmetic or logical operation is logical ZERO when the (n-1)th bit of said result is a logical ONE, said method not dependent on the computed result and comprising the steps of: a) receiving by a group of one-bit cells a first operand, A, having an operand length of at least two bits; b) receiving by said group of one-bit cells a second operand, B, having an operand length of at least two bits; c) computing by an (n-1)th cell of said group of one-bit cells a generate signal G n-1 , from an (n-1)th bit of said first operand, A n-1 , and from an (n-1)th bit of said second operand, B n-1 ; d) receiving by an nth cell of said group of one-bit cells said generate signal G n-1 ; and e) computing by said nth cell of said group of one-bit cells a one-bit-zero signal, Z n , from an nth bit of said first operand, A n , from an nth bit of said second operand, B n , and from said G n-1 wherein said one-bit-zero signal is defined Z n =A n ⊕B n G n-1 .
Claim 2
Independent Claim
206 words
A method of detecting if the nth bit of the result of an arithmetic or logical operation is logical ZERO when the (n-1)th bit of said result is a logical ONE, said method not dependent on the computed result and comprising the steps of: a) receiving by a group of one-bit cells a first operand, A, having an operand length of at least two bits; b) receiving by said group of one-bit cells a second operand, B, having an operand length of at least two bits; c) computing by an (n-1)th cell of said group of one-bit cells a generate signal G n-1 , from an (n-1)th bit of said first operand, A n-1 , and from an (n-1)th bit of said second operand, B n-1 ; d) receiving by an nth cell of said group of one-bit cells said generate signal G n-1 ; and e) computing by said nth cell of said group of one-bit cells a one-bit-zero signal, Z n , from an nth bit of said first operand, A n , from an nth bit of said second operand, B n , and from said G n-1 wherein said one-bit-zero signal is defined Z n =A n ⊕B n G n-1 .
Claim 3
Dependent Claim
71 words
The method of claim 1 and further comprising the step of computing by said (n-1)th cell of said group of one-bit cells a one-bit-one signal, Z n-1 ', from said A n-1 , from said B n-1 , and from a kill signal, K n-2 , from a (n-2)th cell of said group of one-bit cells wherein said one-bit-one signal is defined Z n-1 '=A n-1 ⊕B n-1 K n-2 .
Claim 4
Dependent Claim
28 words
The method of claim 2 and further comprising the step of performing a logical AND on said one-bit-zero signal and said one-bit-one signal to generate an ALU=CONSTANT signal.
Claim 5
Dependent Claim
72 words
The method of claim 1 and further comprising the step of computing by said (n-1)th cell of said group of one-bit cells a one-bit-one signal, Z n-1 ', from said A n-1 , and from said B n-1 , and from a generate signal, G n-2 , from a (n-2)th cell of said group of one-bit cells wherein said one-bit-one signal is defined Z n-1 '=A n-1 ⊕B n-1 ⊕G n-2 .
Claim 6
Dependent Claim
28 words
The method of claim 4 and further comprising the step of performing a logical AND on said one-bit-zero signal and said one-bit-one signal to generate an ALU=CONSTANT signal.
Claim 7
Dependent Claim
19 words
The method of claim 1 wherein n=0 and G n-1 is the carry-in to said group of one-bit cells.
Claim 8
Dependent Claim
26 words
The method of claim 1 wherein said group of one-bit cells receives a first operand, A 0 -A n-1 , having a length of N bits.
Claim 9
Dependent Claim
26 words
The method of claim 1 wherein said group of one-bit cells receives a second operand, B 0 -B n-1 , having a length of N bits.
Claim 10
Independent Claim
207 words
A method of detecting if the nth bit of the result of an arithmetic or logical operation is a logical ONE when the (n-1)th bit of said result is a logical ZERO, said method not dependent on the computed result and comprising the steps of: a) receiving by a group of one-bit cells a first operand, A, having an operand length of at least two bits; b) receiving by said group of one-bit cells a second operand, B, having an operand length of at least two bits; c) computing by an (n-1)th cell of said group of one-bit cells a kill signal K n-1 , from an (n-1)th bit of said first operand, A n-1 , and from an (n-1)th bit of said second operand, B n-1 ; d) receiving by an nth cell of said group of one-bit cells said kill signal K n-1 ; and e) computing by said nth cell of said group of one-bit cells a one-bit-one signal, Z n ', from an nth bit of said first operand, A n , from an nth bit of said second operand, B n , and from said K n-1 wherein said one-bit-one signal is defined Z n '=A n ⊕B n K n-1 .
Claim 11
Independent Claim
207 words
A method of detecting if the nth bit of the result of an arithmetic or logical operation is a logical ONE when the (n-1)th bit of said result is a logical ZERO, said method not dependent on the computed result and comprising the steps of: a) receiving by a group of one-bit cells a first operand, A, having an operand length of at least two bits; b) receiving by said group of one-bit cells a second operand, B, having an operand length of at least two bits; c) computing by an (n-1)th cell of said group of one-bit cells a kill signal K n-1 , from an (n-1)th bit of said first operand, A n-1 , and from an (n-1)th bit of said second operand, B n-1 ; d) receiving by an nth cell of said group of one-bit cells said kill signal K n-1 ; and e) computing by said nth cell of said group of one-bit cells a one-bit-one signal, Z n ', from an nth bit of said first operand, A n , from an nth bit of said second operand, B n , and from said K n-1 wherein said one-bit-one signal is defined Z n '=A n ⊕B n K n-1 .
Claim 12
Dependent Claim
71 words
The method of claim 9 and further comprising the step of computing by said (n-1)th cell of said group of one-bit cells a one-bit-zero signal, Z n-1 , from said A n-1 , from said B n-1 , and from a kill signal, K n-2 , from a (n-2)th cell of said group of one-bit cells wherein said one-bit-zero signal is defined: Z n-1 =A n-1 ⊕B n-1 ⊕K n-2 .
Claim 13
Dependent Claim
28 words
The method of claim 10 and further comprising the step of performing a logical AND on said one-bit-zero signal and said one-bit-one signal to generate an ALU=CONSTANT signal.
Claim 14
Dependent Claim
70 words
The method of claim 9 and further comprising the step of computing by said (n-1)th cell of said group of one-bit cells a one-bit-zero signal, Z n-1 , from said A n-1 , and from said B n-1 , and from a generate signal, G n-2 , from a (n-2)th cell of said group of one-bit cells wherein said one-bit-one signal is defined: Z n-1 ⊕B n-1 G n-2 .
Claim 15
Dependent Claim
28 words
The method of claim 12 and further comprising the step of performing a logical AND on said one-bit-zero signal and said one-bit-one signal to generate an ALU=CONSTANT signal.
Claim 16
Dependent Claim
23 words
The method of claim 9 wherein n=0 and K n-1 is the logical inverse of the carry-in to said group of one-bit cells.
Claim 17
Dependent Claim
26 words
The method of claim 9 wherein said group of one-bit cells receives a first operand, A 0 -A N-1 , having a length of N bits.
Claim 18
Dependent Claim
26 words
The method of claim 9 wherein said group of one-bit cells receives a second operand, B 0 -B N-1 , having a length of N bits.
Claim 19
Independent Claim
207 words
A method of detecting if the nth bit of the result of an arithmetic or logical operation is a logical ONE when the (n-1)th bit of said result is a logical ONE, said method not dependent on the computed result and comprising the steps of: a) receiving by a group of one-bit cells a first operand, A, having an operand length of at least two bits; b) receiving by said group of one-bit cells a second operand, B, having an operand length of at least two bits; c) computing by an (n-1)th cell of said group of one-bit cells a generate signal G n-1 ; from an (n-1)th bit of said first operand, A n-1 , and from an (n-1)th bit of said second operand, B n-1 ; d) receiving by an nth cell of said group of one-bit cells said generate signal G n-1 ; and e) computing by said nth cell of said group of one-bit cells a one-bit-one signal, Z n ', from an nth bit of said first operand, A n , from an nth bit of said second operand, B n , and from said G n-1 wherein said one-bit-one signal is defined Z n '=A n ⊕B n ⊕G n-1 .
Claim 20
Independent Claim
207 words
A method of detecting if the nth bit of the result of an arithmetic or logical operation is a logical ONE when the (n-1)th bit of said result is a logical ONE, said method not dependent on the computed result and comprising the steps of: a) receiving by a group of one-bit cells a first operand, A, having an operand length of at least two bits; b) receiving by said group of one-bit cells a second operand, B, having an operand length of at least two bits; c) computing by an (n-1)th cell of said group of one-bit cells a generate signal G n-1 ; from an (n-1)th bit of said first operand, A n-1 , and from an (n-1)th bit of said second operand, B n-1 ; d) receiving by an nth cell of said group of one-bit cells said generate signal G n-1 ; and e) computing by said nth cell of said group of one-bit cells a one-bit-one signal, Z n ', from an nth bit of said first operand, A n , from an nth bit of said second operand, B n , and from said G n-1 wherein said one-bit-one signal is defined Z n '=A n ⊕B n ⊕G n-1 .
Claim 21
Dependent Claim
70 words
The method of claim 17 and further comprising the step of computing by said (n-1)th cell of said group of one-bit cells a one-bit-one signal, Z n-1 ', from said A n-1 , from B n-1 , and from a kill signal, K n-2 , from a (n-2)th cell of said group of one-bit cells wherein said one-bit-one signal is defined Z n-1 '=A n-1 ⊕B n-1 K n-2 .
Claim 22
Dependent Claim
34 words
The method of claim 18 and further comprising the step of performing a logical AND on said one-bit-one signal, Z n ', and said one-bit-one signal, Z n-1 ', to generate an ALU=CONSTANT signal.
Claim 23
Dependent Claim
72 words
The method of claim 17 and further comprising the step of computing by said (n-1)th cell of said group of one-bit cells a one-bit-one signal, Z n-1 ', from said A n-1 , and from said B n-1 , and from a generate signal, G n-2 , from a (n-2)th cell of said group of one-bit cells wherein said one-bit-one signal is defined Z n-1 '=A n-1 ⊕B n-1 ⊕G n-2 .
Claim 24
Dependent Claim
34 words
The method of claim 20 and further comprising the step of performing a logical AND on said one-bit-one signal, Z n ', and said one-bit-one signal, Z n-1 ', to generate an ALU=CONSTANT signal.
Claim 25
Dependent Claim
19 words
The method of claim 17 wherein n=0 and G n-1 is the carry-in to said group of one-bit cells.
Claim 26
Dependent Claim
26 words
The method of claim 17 wherein said group of one-bit cells receives a first operand, A 0 -A N-1 , having a length of N bits.
Claim 27
Dependent Claim
26 words
The method of claim 17 wherein said group of one-bit cells receives a second operand, B 0 -B N-1 , having a length of N bits.
Claim 28
Independent Claim
337 words
A method of detecting a selected condition of a subfield R 0 -R N-1 of a pending result for an arithmetic or logical operation, said method comprising the steps of: a) receiving by a group of one-bit cells a first operand, A, having an operand length of at least two bits; b) receiving by said group of one-bit cells a second operand, B, having an operand length of at least two bits; c) receiving by one of said group of one-bit cells a first signal, X n-1 ; d) computing a second signal, X n , from an nth bit of said first operand, A n , and an nth bit of said second operand, B n wherein said second signal, X n is a function of said A n and B n ; e) receiving by another one of said group of one-bit cells said second signal, X n ; f) computing by said one of said group of one-bit cells a first one-bit-result signal, Y n , from said A n , said B n , and from said X n-1 ; g) computing by said another one of said group of one-bit cells a second one-bit-result signal, Y n+1 , from an (n+1)th bit of said first operand, A n+1 , an (n+1)th bit of said second operand, B n+1 , and from said X n ; h) receiving by a first combinatorial circuit said first one-bit-result signal Y n ; i) receiving by said first combinatorial circuit said second one-bit-result signal Y n+1 ; j) computing by said first combinatorial circuit a SUBALU=0 signal from said first one-bit-result signal Y n and said second one-bit-result signal, Y n+1 ; k) receiving by a second combinatorial logic circuit said SUBALU=0 signal; l) receiving by said second combinatorial logic circuit a subfield least significant bit result R n-1 ; and m) computing by said second combinatorial circuit a SUBFIELD=CONSTANT signal from said first one-bit-result signal Y n and said second one-bit-result signal, Y n+1 .
Claim 29
Independent Claim
337 words
A method of detecting a selected condition of a subfield R 0 -R N-1 of a pending result for an arithmetic or logical operation, said method comprising the steps of: a) receiving by a group of one-bit cells a first operand, A, having an operand length of at least two bits; b) receiving by said group of one-bit cells a second operand, B, having an operand length of at least two bits; c) receiving by one of said group of one-bit cells a first signal, X n-1 ; d) computing a second signal, X n , from an nth bit of said first operand, A n , and an nth bit of said second operand, B n wherein said second signal, X n is a function of said A n and B n ; e) receiving by another one of said group of one-bit cells said second signal, X n ; f) computing by said one of said group of one-bit cells a first one-bit-result signal, Y n , from said A n , said B n , and from said X n-1 ; g) computing by said another one of said group of one-bit cells a second one-bit-result signal, Y n+1 , from an (n+1)th bit of said first operand, A n+1 , an (n+1)th bit of said second operand, B n+1 , and from said X n ; h) receiving by a first combinatorial circuit said first one-bit-result signal Y n ; i) receiving by said first combinatorial circuit said second one-bit-result signal Y n+1 ; j) computing by said first combinatorial circuit a SUBALU=0 signal from said first one-bit-result signal Y n and said second one-bit-result signal, Y n+1 ; k) receiving by a second combinatorial logic circuit said SUBALU=0 signal; l) receiving by said second combinatorial logic circuit a subfield least significant bit result R n-1 ; and m) computing by said second combinatorial circuit a SUBFIELD=CONSTANT signal from said first one-bit-result signal Y n and said second one-bit-result signal, Y n+1 .
Claim 30
Dependent Claim
36 words
The method of claim 25 wherein said first signal, X n-1 , is a first kill signal, K n-1 , and said first one-bit-result signal, Y n , is a first one-bit-zero signal, Z n .
Claim 31
Dependent Claim
36 words
The method of claim 25 wherein said first signal, X n-1 , is a first kill signal, K n-1 , and said first one-bit-result signal, Y n , is a first one-bit-one signal, Z n '.
Claim 32
Dependent Claim
36 words
The method of claim 25 wherein said second signal, X n , is a second kill signal, K n , and said second one-bit-result signal, Y n+1 , is a second one-bit-zero signal, Z n+1 .
Claim 33
Dependent Claim
36 words
The method of claim 25 wherein said second signal, X n , is a second kill signal, K n , and said second one-bit-result signal, Y n+1 , is a second one-bit-one signal, Z n+1 '.
Claim 34
Dependent Claim
36 words
The method of claim 25 wherein said first signal, X n-1 , is a first generate signal, G n-1 , and said first one-bit-result signal, Y n , is a first one-bit-zero signal, Z n .
Claim 35
Dependent Claim
36 words
The method of claim 25 wherein said first signal, X n+1 , is a first generate signal, G n-1 , and said first one-bit-result signal, Y n , is a first one-bit-one signal, Z n '.
Claim 36
Dependent Claim
36 words
The method of claim 25 wherein said second signal, X n , is a second generate signal, G n , and said second one-bit-result signal, Y n+1 , is a second one-bit-zero signal, Z n+1 .
Claim 37
Dependent Claim
36 words
The method of claim 25 wherein said second signal, X n , is a second generate signal, G n , and said second one-bit-result signal, Y n+1 , is a second one-bit-one signal, Z n+1 '.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |