US4831570A
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Method of and circuit for generating bit-order modified binary signals
Assignee: Texas Instruments Inc
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Filing: 1986-11-26
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Granted: 1989-05-16
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Expires: 2006-11-26
Abstract
Abstract A method of and a circuit for generating address signals, wherein a binary index signal and a binary base address signal are stored in index and address registers, respectively, whereupon the index signal and the base address signal are added together to produce an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation. The initial output address signal is tentatively storing in the address register and is added to the index signal to produce an output address signal differing in bit pattern from the initial output address signal during the cycle of signal generating operation immediately subsequent to the initial cycle. This output signal is likewise tentatively storing in the signal register and thereafter the index signal from the index register and the output address signal produced during each of the successive cycles of signal generating operation are added together to produce another output address signal differing in bit pattern from each of the output address signals produced during the immediately preceding cycle of signal generating operation, wherein the arithmetic sum is produced by carrying out a forward arithmetic addition from the least significant bits forward or a reverse arithmetic addition from the most significant bits backward.
Inventors
- 👤 Shigeshi Abiko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:45
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5055; G06F17/00; G06F17/10; G06F17/14; G06F17/141; G06F17/142; G06F7/501; G06F7/503; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3852
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
203 words
A method of generating binary signals comprising: (a) storing in a first memory, binary index signal comprising a sequence of a predetermined number of bits, (b) storing in a second memory, a binary base signal comprising a sequence of said predetermined number of bits, (c) carrying out a reverse arithmetic addition from the most significant bits of said index signal and said base signal for producing an initial output signal representative of the arithmetic sum of the index and base signals during an initial cycle of signal generating operation, (d) Storing said initial output signal in said second memory and adding the initial output signal to said index signal to produce an output signal differing in bit pattern from said initial output signal during the cycle of signal generating operation immediately subsequent to said initial cycle and storing the last named output signal in said second memory, and (e) thereafter carrying out a reverse arithmetic addition of said index signal from said first memory and the output signal produced during each of the successive cycles of signal generating operation to produce another signal differing in bit pattern from each of the output signals produced during the immediately preceding cycle of signal generating operation.
Claim 2
Independent Claim
203 words
A method of generating binary signals comprising: (a) storing in a first memory, binary index signal comprising a sequence of a predetermined number of bits, (b) storing in a second memory, a binary base signal comprising a sequence of said predetermined number of bits, (c) carrying out a reverse arithmetic addition from the most significant bits of said index signal and said base signal for producing an initial output signal representative of the arithmetic sum of the index and base signals during an initial cycle of signal generating operation, (d) Storing said initial output signal in said second memory and adding the initial output signal to said index signal to produce an output signal differing in bit pattern from said initial output signal during the cycle of signal generating operation immediately subsequent to said initial cycle and storing the last named output signal in said second memory, and (e) thereafter carrying out a reverse arithmetic addition of said index signal from said first memory and the output signal produced during each of the successive cycles of signal generating operation to produce another signal differing in bit pattern from each of the output signals produced during the immediately preceding cycle of signal generating operation.
Claim 3
Independent Claim
208 words
A method of sequentially generating binary address signals comprising: (a) storing in a first register, a binary index signal comprising a sequence of a predetermined number of bits, (b) storing in a second register, a binary base address signal comprising a sequence of said predetermined number of bits, (c) carrying out a reverse arithmetic addition from the most significant bits of said index signal and said base address signal for producing an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation, (d) storing said initial output address signal in said second register and adding the initial output address signal to said index signal for producing an output address signal differing in bit pattern from said initial output address signal during the cycle of signal generating operation immediately subsequent to said initial cycle and storing the last named output address signal in said second register, and (e) thereafter carrying out a reverse arithmetic addition of said index signal from said first register and the output address signal produced during each of the successive cycles of signal generating operation for producing another output address signals produced during the immediately preceding cycle of signal generating operation.
Claim 4
Independent Claim
208 words
A method of sequentially generating binary address signals comprising: (a) storing in a first register, a binary index signal comprising a sequence of a predetermined number of bits, (b) storing in a second register, a binary base address signal comprising a sequence of said predetermined number of bits, (c) carrying out a reverse arithmetic addition from the most significant bits of said index signal and said base address signal for producing an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation, (d) storing said initial output address signal in said second register and adding the initial output address signal to said index signal for producing an output address signal differing in bit pattern from said initial output address signal during the cycle of signal generating operation immediately subsequent to said initial cycle and storing the last named output address signal in said second register, and (e) thereafter carrying out a reverse arithmetic addition of said index signal from said first register and the output address signal produced during each of the successive cycles of signal generating operation for producing another output address signals produced during the immediately preceding cycle of signal generating operation.
Claim 5
Dependent Claim
221 words
A bit-order modifiable signal generator circuit, comprising (a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network, (b) an index register operable for having programmably yet fixedly stored therein a binary index signal comprising a sequence of a predetermined number of bits, and (c) a signal register operable for having programmably yet fixedly stored therein a binary base signal comprising a sequence of said predetermined number of bits, (d) said adder circuit being responsive to the index signal output from said index register and to a binary signal output from said signal register for producing an output signal representative of the arithmetic sum of the index signal and the signal output from the signal register during each cycle of signal generating operation, and (e) said signal register being responsive to said output signal from said adder circuit for tentatively storing the output signal from the adder circuit and feeding back the signal to said adder circuit for being arithmetically added to said index signal during each cycle of signal generating operation.
Claim 6
Dependent Claim
221 words
A bit-order modifiable signal generator circuit, comprising (a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network, (b) an index register operable for having programmably yet fixedly stored therein a binary index signal comprising a sequence of a predetermined number of bits, and (c) a signal register operable for having programmably yet fixedly stored therein a binary base signal comprising a sequence of said predetermined number of bits, (d) said adder circuit being responsive to the index signal output from said index register and to a binary signal output from said signal register for producing an output signal representative of the arithmetic sum of the index signal and the signal output from the signal register during each cycle of signal generating operation, and (e) said signal register being responsive to said output signal from said adder circuit for tentatively storing the output signal from the adder circuit and feeding back the signal to said adder circuit for being arithmetically added to said index signal during each cycle of signal generating operation.
Claim 7
Dependent Claim
58 words
The bit-order modifiable signal generator circuit according to claim 3 wherein the forward-reverse selective carry propagation network comprises: a reverse propagator for propagating a reverse carry; a forward propagator for propagating a forward carry; and a forward-reverse selector circuit operatively connected to the reverse propagator and the forward propagator for selecting the reverse propagator and the forward propagator.
Claim 8
Dependent Claim
52 words
The bit-order modifiable signal generator circuit according to claim 3 wherein the forward-reverse selective carry propagation network comprises: a bi-directional carry propagator for propagating a forward carry and a reverse carry; and a forward-reverse selector circuit operatively connected to said bi-directional carry propagator for selecting the reverse carry and the forward carry.
Claim 9
Dependent Claim
273 words
A bit-order modifiable address generator circuit having functions to perform a fast Fourier transform algorithm with a predetermined number of sample points set therein, comprising (a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network, (b) an index register operable for having programmably yet fixedly stored therein a binary index address signal comprising a sequence of a predetermined number of bits, the predetermined number of bits being uniquely determined depending upon said predetermined number of sample points set in said fast Fourier transform algorithm, and (c) an address register operable for having programmably yet fixedly stored therein a binary base address signal comprising a sequence of said predetermined number of bits, (d) said adder circuit being responsive to the index address signal output from said index register and to a binary address signal output from said address register for producing an output address signal representative of the arithmetic sum of the index address signal and the address signal output from the address register during each cycle of address generating operation, and (e) said address register being responsive to said output address signal from said adder circuit for tentatively storing the output address signal from the adder circuit and feeding back the address signal to said adder circuit for being arithmetically added to said index address signal during each cycle of address generating operation.
Claim 10
Dependent Claim
273 words
A bit-order modifiable address generator circuit having functions to perform a fast Fourier transform algorithm with a predetermined number of sample points set therein, comprising (a) an adder circuit comprising the combination of a binary multi-stage adder/subtractor and a forward-reverse selective carry propagation network, the multi-stage adder/subtractor having functions to carry out both a forward arithmetic addition from the least significant bits forward and a reverse arithmetic addition from the most significant bits backward selectively under the control of said forward/reverse selective carry propagation network, (b) an index register operable for having programmably yet fixedly stored therein a binary index address signal comprising a sequence of a predetermined number of bits, the predetermined number of bits being uniquely determined depending upon said predetermined number of sample points set in said fast Fourier transform algorithm, and (c) an address register operable for having programmably yet fixedly stored therein a binary base address signal comprising a sequence of said predetermined number of bits, (d) said adder circuit being responsive to the index address signal output from said index register and to a binary address signal output from said address register for producing an output address signal representative of the arithmetic sum of the index address signal and the address signal output from the address register during each cycle of address generating operation, and (e) said address register being responsive to said output address signal from said adder circuit for tentatively storing the output address signal from the adder circuit and feeding back the address signal to said adder circuit for being arithmetically added to said index address signal during each cycle of address generating operation.
Claim 11
Dependent Claim
58 words
The bit-order modifiable address generator circuit according to claim 6 wherein the forward-reverse selective carry propagation network comprises: a reverse propagator for propagating a reverse carry; a forward propagator for propagating a forward carry; and a forward-reverse selector circuit operatively connected to the reverse propagator and the forward propagator for selecting the reverse propagator and the forward propagator.
Claim 12
Dependent Claim
53 words
The bit-order modifiable address generator circuit according to claim 6 wherein the forward-reverse selective carry propagation network comprises: a bi-directional carry propagator for selectively propagating a forward carry and a reverse carry; and a forward-reverse selector circuit operatively connected to the bidirectional carry propagator for selecting the reverse carry and the forward carry.
Claim 13
Dependent Claim
115 words
A bit-order modifiable generator circuit comprising: an adder comprising a multistage adder circuit and a forward reverse selective carry propagation network, the multistage adder circuit including means for selectively performing a reverse arithmetic addition from the most significant bits selectively under the control of the forward-reverse select carry propagation network; a first register having stored therein a first signal having a predetermined number of bits and the first register being operatively connected to provide a first input to the adder; and a second register operatively connected to receive and store a sum signal from the adder, to provide a second input to the adder and to provide as an output the generated bit-order modified signal.
Claim 14
Dependent Claim
115 words
A bit-order modifiable generator circuit comprising: an adder comprising a multistage adder circuit and a forward reverse selective carry propagation network, the multistage adder circuit including means for selectively performing a reverse arithmetic addition from the most significant bits selectively under the control of the forward-reverse select carry propagation network; a first register having stored therein a first signal having a predetermined number of bits and the first register being operatively connected to provide a first input to the adder; and a second register operatively connected to receive and store a sum signal from the adder, to provide a second input to the adder and to provide as an output the generated bit-order modified signal.
Claim 15
Dependent Claim
39 words
The bit-order modifiable signal generator circuit according to claim 9 wherein the multistage adder circuit further includes means, selectively controlled by the forward-reverse selective carry propagation network, for selectively performing a forward arithmetic addition from the least significant bits.
Claim 16
Dependent Claim
58 words
The bit-order modifiable signal generator circuit according to claim 10 wherein the forward-reverse selective carry propagation network comprises: a reverse propagator for propagating a reverse carry; a forward propagator for propagating a forward carry; and a forward-reverse selector circuit operatively connected to the reverse propagator and the forward propagator for selecting the reverse propagator and the forward propagator.
Claim 17
Dependent Claim
52 words
The bit-order modifiable signal generator circuit according to claim 10 wherein the forward-reverse selective carry propagation network comprises: a bi-directional carry propagator for propagating a forward carry and a reverse carry; and a forward-reverse selector circuit operatively connected to the bi-directional carry propagator for selecting the reverse carry and the forward carry.
Claim 18
Dependent Claim
19 words
The bit-order modifiable signal generator circuit according to claim 9 wherein both said first and second registers are programmable.
Claim 19
Dependent Claim
29 words
The bit-order modifiable signal generator circuit according to claim 9 wherein the generated bit-order modified signal is an address signal for use in performing a fast Fourier transform algorithm.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |