Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators

Claim 1

A method for forming an interconnect structure on a semiconductor body, comprising the steps of: a. forming a plurality of spaced interconnect lines on said semiconductor body; b. filling the space between all adjacent interconnect lines having a distance therebetween no greater than a given distance with an insulating material having a dielectric constant lower than the dielectric constant of silicon dioxide and greater than or equal to one, and leaving an unfilled open field area between adjacent interconnect lines having a distance therebetween greater than said given distance; c. depositing a first layer of silicon dioxide over said interconnect lines, said open field area and said insulating material.

Claim 2

A method for forming an interconnect structure on a semiconductor body, comprising the steps of: a. forming a plurality of spaced interconnect lines on said semiconductor body; b. filling the space between all adjacent interconnect lines having a distance therebetween no greater than a given distance with an insulating material having a dielectric constant lower than the dielectric constant of silicon dioxide and greater than or equal to one, and leaving an unfilled open field area between adjacent interconnect lines having a distance therebetween greater than said given distance; c. depositing a first layer of silicon dioxide over said interconnect lines, said open field area and said insulating material.

Claim 3

A method of forming a multi-level metal interconnect having reduced line-to-line capacitance on a semiconductor body, comprising the steps of: a. depositing a first layer of metal over said semiconductor body; b. etching said first metal layer to form a first plurality of spaced interconnect lines, some of said first plurality of interconnect lines being spaced from some other of said first plurality of interconnect lines by a distance of W and some of said first plurality of interconnect lines being spaced from other of said first plurality of interconnect lines by a distance of W' where W is greater than W'; c. depositing a first organic polymer layer over said semiconductor body and said first plurality of interconnect lines to a thickness less than W divided by twice the step coverage said organic polymer having a dielectric constant less than 3.9 and greater than or equal to one; d. etching said first organic polymer layer back to expose an upper surface of said first plurality of interconnect lines and an open field area on said semiconductor body comprising the region between adjacent interconnect lines separated by more than W'; e. depositing a first silicon dioxide layer over said first plurality of interconnect lines, said open field area and said first organic polymer layer; f. planarizing said first silicon dioxide layer; g. selectively etching contact holes through said first silicon dioxide layer to at least some of said first plurality of interconnect lines; and h. filling said contact holes with a second layer of metal. i. depositing a third layer of metal over said first silicon dioxide layer; j. etching said third metal layer to form a second plurality of spaced interconnect lines, some of said second plurality of interconnect lines being spaced from some other of said second plurality of interconnect lines by a distance of W and some of said second plurality of interconnect lines being spaced from other of said second plurality of interconnect lines by a distance of W' where W is greater than W'; k. depositing a second organic polymer layer over said first silicon dioxide layer and said second plurality of interconnect lines to a thickness less than W divided by twice the step coverage, said second organic polymer layer having a dielectric constant less than 3.9 and greater than or equal to one; l. etching said second organic polymer layer back to expose an upper surface of said second plurality of interconnect lines and at least a portion of said first silicon dioxide layer disposed between two of said second plurality of spaced interconnect lines comprising a second open field area between adjacent interconnect lines in said second plurality of interconnect lines separated by more than W'; m. depositing a second silicon dioxide layer over said second plurality of interconnect lines, said exposed first silicon dioxide layer and said second organic polymer layer; and n. planarizing said second silicon dioxide layer.

Claim 4

A method of forming a multi-level metal interconnect having reduced line-to-line capacitance on a semiconductor body, comprising the steps of: a. depositing a first layer of metal over said semiconductor body; b. etching said first metal layer to form a first plurality of spaced interconnect lines, some of said first plurality of interconnect lines being spaced from some other of said first plurality of interconnect lines by a distance of W and some of said first plurality of interconnect lines being spaced from other of said first plurality of interconnect lines by a distance of W' where W is greater than W'; c. depositing a first organic polymer layer over said semiconductor body and said first plurality of interconnect lines to a thickness less than W divided by twice the step coverage said organic polymer having a dielectric constant less than 3.9 and greater than or equal to one; d. etching said first organic polymer layer back to expose an upper surface of said first plurality of interconnect lines and an open field area on said semiconductor body comprising the region between adjacent interconnect lines separated by more than W'; e. depositing a first silicon dioxide layer over said first plurality of interconnect lines, said open field area and said first organic polymer layer; f. planarizing said first silicon dioxide layer; g. selectively etching contact holes through said first silicon dioxide layer to at least some of said first plurality of interconnect lines; and h. filling said contact holes with a second layer of metal. i. depositing a third layer of metal over said first silicon dioxide layer; j. etching said third metal layer to form a second plurality of spaced interconnect lines, some of said second plurality of interconnect lines being spaced from some other of said second plurality of interconnect lines by a distance of W and some of said second plurality of interconnect lines being spaced from other of said second plurality of interconnect lines by a distance of W' where W is greater than W'; k. depositing a second organic polymer layer over said first silicon dioxide layer and said second plurality of interconnect lines to a thickness less than W divided by twice the step coverage, said second organic polymer layer having a dielectric constant less than 3.9 and greater than or equal to one; l. etching said second organic polymer layer back to expose an upper surface of said second plurality of interconnect lines and at least a portion of said first silicon dioxide layer disposed between two of said second plurality of spaced interconnect lines comprising a second open field area between adjacent interconnect lines in said second plurality of interconnect lines separated by more than W'; m. depositing a second silicon dioxide layer over said second plurality of interconnect lines, said exposed first silicon dioxide layer and said second organic polymer layer; and n. planarizing said second silicon dioxide layer.

Claim 13

A method of forming a multi-level metal interconnect having reduced line-to-line capacitance on a semiconductor body, comprising the steps of: a. depositing a first layer of metal over said semiconductor body; b. etching said first metal layer to form a first plurality of spaced interconnect lines; c. depositing a first organic polymer layer over said semiconductor body and said first plurality of interconnect lines to a thickness less than a selected interconnect spacing divided by twice the step coverage, said organic polymer having a dielectric constant less than 3.9 and greater than or equal to one; d. etching said first organic polymer layer back to expose an upper surface of said first plurality of interconnect lines, said organic polymer between interconnect lines separated by less than said selected interconnect spacing and an open field area on said semiconductor body comprising the region between adjacent interconnect lines separated by more than said selected interconnect spacing; e. depositing a first silicon dioxide layer over said first plurality of interconnect lines, said open field area and said first organic polymer layer; f. planarizing said first silicon dioxide layer; g. etching contact holes through said first silicon dioxide layer to at least some of said first plurality of interconnect lines; and h. filling said contact holes with a second layer of metal.

Claim 14

A method of forming a multi-level metal interconnect having reduced line-to-line capacitance on a semiconductor body, comprising the steps of: a. depositing a first layer of metal over said semiconductor body; b. etching said first metal layer to form a first plurality of spaced interconnect lines; c. depositing a first organic polymer layer over said semiconductor body and said first plurality of interconnect lines to a thickness less than a selected interconnect spacing divided by twice the step coverage, said organic polymer having a dielectric constant less than 3.9 and greater than or equal to one; d. etching said first organic polymer layer back to expose an upper surface of said first plurality of interconnect lines, said organic polymer between interconnect lines separated by less than said selected interconnect spacing and an open field area on said semiconductor body comprising the region between adjacent interconnect lines separated by more than said selected interconnect spacing; e. depositing a first silicon dioxide layer over said first plurality of interconnect lines, said open field area and said first organic polymer layer; f. planarizing said first silicon dioxide layer; g. etching contact holes through said first silicon dioxide layer to at least some of said first plurality of interconnect lines; and h. filling said contact holes with a second layer of metal.