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Patent US5485473A successfully refreshed from Google Patents.
US5485473A
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Method and system for testing an integrated circuit featuring scan design
Assignee: International Business Machines Corp
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Filing: 1993-08-20
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Granted: 1996-01-16
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Expires: 2013-08-20
Abstract
Abstract The present invention provides for improved testing of an integrated circuit. In order to measure a test signal S from the integrated circuit 1 a multi-pattern is placed in a shift register. The multi-pattern is generated by overlaying at least two test patterns Ax and Bx. Therefore the signal S changes its state in response to only a small amount of shift operations.
Inventors
- 👤 Ulich Diebold
- 👤 Peter Rost
- 👤 Manfred Schmidt
- 👤 Otto Torreiter
- 👤 Rolf Vogt
- 👤 Klaus Wagner-Drebenstedt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G01R31/302; G01R31/305; G01R31/307
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
113 words
A method of testing circuitry including at least one shift register, comprising the steps of: (a) inputting an X+A-bit test signal pattern into the shift register; (b) forming an input test signal pattern of X bits by recirculating said X+A-bit test signal pattern; (c) shifting said X-bit input test signal pattern from the shift register to the circuitry under test and carrying out a first test; (d) shifting said X+A-bit test signal pattern in the shift register by Y bits (1≦Y<X) to input a new X-bit test signal pattern to the circuit under test and carrying out a second test; (e) repeating step (d) N times (N≧0) to carry out N additional tests.
Claim 2
Independent Claim
113 words
A method of testing circuitry including at least one shift register, comprising the steps of: (a) inputting an X+A-bit test signal pattern into the shift register; (b) forming an input test signal pattern of X bits by recirculating said X+A-bit test signal pattern; (c) shifting said X-bit input test signal pattern from the shift register to the circuitry under test and carrying out a first test; (d) shifting said X+A-bit test signal pattern in the shift register by Y bits (1≦Y<X) to input a new X-bit test signal pattern to the circuit under test and carrying out a second test; (e) repeating step (d) N times (N≧0) to carry out N additional tests.
Claim 3
Dependent Claim
80 words
The method according to claim 1, wherein prior to step (a) said X+A-bit test signal pattern is generated from a set of X-bit test signal patterns by a method comprising the steps of: (a) sequentially selecting and offsetting selected ones of said set of X-bit test signal patterns by up to y bit positions (1≦Y<X) with respect to one another; and (b) overlaying said set of X-bit test signal patterns on one another as selected and offset in step (a).
Claim 4
Dependent Claim
52 words
The method according to claim 1, wherein prior to step (a) said X+A-bit test signal pattern is formed from N X-bit test signal patterns, said X-bit test signal patterns being offset with respect to one another such that all bits to be overlaid on one another are of the same logic state.
Claim 5
Dependent Claim
51 words
The method according to claim 2, wherein at least some of said X-bit test signal patterns have "don't care" bits, and wherein said X-bit test signal patterns are offset such that all bits to be overlaid on one another are either of the same logic state or are "don't care" bits.
Claim 6
Dependent Claim
168 words
The method according to claim 4, wherein said first and second X-bit test signal patterns, each having a plurality of data bits set at first or second logic states and at least one "don't care" bit at respective bit positions, are combined to form a single composite signal, by a method comprising the steps of: (a) offsetting said second X-bit signal test pattern with respect to said first X-bit signal test pattern by at least one bit position, so that a bit in said second X-bit signal test pattern at the first bit position is aligned with a bit in said first X-bit signal test pattern at one of a second, third . . . X-bit position, such that the respective bits of said first and second X-bit signals as aligned are either of the same logic state or of different logic states wherein one or both bits is a "don't care" bit; (b) overlaying the first and second X-bit signal test patterns as offset on one another.
Claim 7
Dependent Claim
31 words
The method recited in claim 5, wherein the second X-bit signal test pattern is offset with respect to the first X-bit signal test pattern by not more than two bit positions.
Claim 8
Dependent Claim
26 words
The method as recited in claim 2, wherein every one of said set of X-bit signal test patterns are selected, offset, and overlaid on one another.
Claim 9
Independent Claim
115 words
A method of testing an integrated circuit featuring scan design such as LSSD or boundary scan, including at least one scan path, comprising the steps of: (a) forming a test signal pattern in a shift register; (b) inputting a contiguous portion of the test signal pattern in the shift register into the scan path; (c) measuring a response S of the integrated circuit to the test signal pattern in (b); (d) inputting a different contiguous portion of the test pattern in the shift register into the scan path by recirculating said test signal pattern in the shift register so that the measured signal S of the cone changes its logic state from that in (b).
Claim 10
Independent Claim
115 words
A method of testing an integrated circuit featuring scan design such as LSSD or boundary scan, including at least one scan path, comprising the steps of: (a) forming a test signal pattern in a shift register; (b) inputting a contiguous portion of the test signal pattern in the shift register into the scan path; (c) measuring a response S of the integrated circuit to the test signal pattern in (b); (d) inputting a different contiguous portion of the test pattern in the shift register into the scan path by recirculating said test signal pattern in the shift register so that the measured signal S of the cone changes its logic state from that in (b).
Claim 11
Dependent Claim
24 words
The method according to claim 8, wherein said response S of the integrated circuit to said input test patterns is measured by contactless techniques.
Claim 12
Dependent Claim
29 words
The method according to claim 9, further comprising the step of statistically analyzing said measured response S by repeatedly adding the results of measurements from each respective test pattern.
Claim 13
Dependent Claim
18 words
The method according to claim 10, wherein said statistical analysis is performed separately for each input test pattern.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |