US5485104A
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US
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Logic allocator for a programmable logic device
Assignee: Lattice Semiconductor Corp
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Filing: 1995-01-18
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Granted: 1996-01-16
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Expires: 2015-01-18
Abstract
Abstract Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.
Inventors
- 👤 Om P. Agrawal
- 👤 Jerry D. Moench
- 👤 Kerry A. Ilgenstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17724; H03K19/17728; H03K19/17736; H03K19/1774; H03K19/17744
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
114 words
A programmable logic device comprising: a programmable product term array having output lines; and programmable logic allocator means, operatively coupled to said programmable product term array output lines, for selectively coupling and decoupling a set of said programmable product term array output lines to one output line in a multiplicity of output lines of said logic allocator means wherein upon coupling said set of said programmable product term array output lines to said one output line in said multiplicity of output lines of said logic allocator means, said set of programmable product term array output lines are unavailable to all other output lines in said multiplicity of output lines of said logic allocator means.
Claim 2
Dependent Claim
114 words
A programmable logic device comprising: a programmable product term array having output lines; and programmable logic allocator means, operatively coupled to said programmable product term array output lines, for selectively coupling and decoupling a set of said programmable product term array output lines to one output line in a multiplicity of output lines of said logic allocator means wherein upon coupling said set of said programmable product term array output lines to said one output line in said multiplicity of output lines of said logic allocator means, said set of programmable product term array output lines are unavailable to all other output lines in said multiplicity of output lines of said logic allocator means.
Claim 3
Dependent Claim
69 words
The programmable logic device of claim 1 wherein said programmable logic allocator means comprises a multiplicity of programmable demultiplexers with each demultiplexer having an input terminal and a multiplicity of output terminals, wherein said input terminal of said demultiplexer is coupled to said set of said programmable product term array output lines and each demultiplexer output terminal is connected to a different output line of said logic allocator means.
Claim 4
Independent Claim
79 words
A method for coupling and decoupling a product term array from logic macrocells comprising: coupling a set of product terms to an input terminal of a programmable demultiplexer; and connecting each output terminal of the programmable demultiplexer to a different logic macrocell wherein upon coupling said input terminal to one of said logic macrocells, the set of product terms coupled to said input terminal are unavailable to the remaining logic macrocells connected to the remaining terminals of said demultiplexer.
Claim 5
Independent Claim
79 words
A method for coupling and decoupling a product term array from logic macrocells comprising: coupling a set of product terms to an input terminal of a programmable demultiplexer; and connecting each output terminal of the programmable demultiplexer to a different logic macrocell wherein upon coupling said input terminal to one of said logic macrocells, the set of product terms coupled to said input terminal are unavailable to the remaining logic macrocells connected to the remaining terminals of said demultiplexer.
Claim 6
Dependent Claim
49 words
The method of claim 3 further comprising the step of connecting each logic macrocell to an output terminal of each of a multiplicity of programmable demultiplexers so that the logic macrocell is programmably couplable to from zero to a predetermined number of product terms from said product term array.
Claim 7
Independent Claim
68 words
A method for coupling and decoupling a programmable array from logic macrocells comprising: connecting output lines of said programmable array to a logic allocator; and configuring said logic allocator to connect signals from a group of said output lines of said programmable array to one logic macrocell, and the disconnect said signals on said group of said output lines of said programmable array from all other logic macrocells.
Claim 8
Independent Claim
68 words
A method for coupling and decoupling a programmable array from logic macrocells comprising: connecting output lines of said programmable array to a logic allocator; and configuring said logic allocator to connect signals from a group of said output lines of said programmable array to one logic macrocell, and the disconnect said signals on said group of said output lines of said programmable array from all other logic macrocells.
Claim 9
Dependent Claim
108 words
A programmable logic device comprising: a programmable array having a plurality of output lines; a plurality of programmable logic macrocells, each programmable logic macrocell having at least one input line; and a logic allocator operatively coupled to said plurality of programmable array output lines, and selectively operatively coupled to and decoupled from each of said plurality of programmable logic macrocells; wherein said logic allocator couples a plurality of output signals on said plurality of programmable array output lines to selected input lines of said plurality of programmable logic macrocells; and said logic allocator decouples unselected input lines of said plurality of programmable logic macrocells from said programmable array.
Claim 10
Dependent Claim
108 words
A programmable logic device comprising: a programmable array having a plurality of output lines; a plurality of programmable logic macrocells, each programmable logic macrocell having at least one input line; and a logic allocator operatively coupled to said plurality of programmable array output lines, and selectively operatively coupled to and decoupled from each of said plurality of programmable logic macrocells; wherein said logic allocator couples a plurality of output signals on said plurality of programmable array output lines to selected input lines of said plurality of programmable logic macrocells; and said logic allocator decouples unselected input lines of said plurality of programmable logic macrocells from said programmable array.
Claim 11
Dependent Claim
155 words
In a programmable logic device, a structure comprising: a first logic gate having an output line; a second logic gate having a plurality of input lines and an output line; a third logic gate having a plurality of input lines and an output line; and a first programmable demultiplexer having; an input terminal connected to said output line of said first logic gate; a first output terminal connected to one input line in said plurality of input lines of said second logic gate; and a second output terminal connected to one input line in said plurality of input lines of said third logic gate; wherein said first programmable demultiplexer programmably connects said first programmable demultiplexer input terminals to one of said first and second output terminals of said first programmable demultiplexer, and programmably disconnects said first programmable demultiplexer input terminal from the other of said first and second output terminals of said first programmable demultiplexer.
Claim 12
Dependent Claim
155 words
In a programmable logic device, a structure comprising: a first logic gate having an output line; a second logic gate having a plurality of input lines and an output line; a third logic gate having a plurality of input lines and an output line; and a first programmable demultiplexer having; an input terminal connected to said output line of said first logic gate; a first output terminal connected to one input line in said plurality of input lines of said second logic gate; and a second output terminal connected to one input line in said plurality of input lines of said third logic gate; wherein said first programmable demultiplexer programmably connects said first programmable demultiplexer input terminals to one of said first and second output terminals of said first programmable demultiplexer, and programmably disconnects said first programmable demultiplexer input terminal from the other of said first and second output terminals of said first programmable demultiplexer.
Claim 13
Dependent Claim
132 words
In a programmable logic device, a structure as in claim 7 further comprising: a fourth logic gate having an output line; and a second programmable demultiplexer having: an input terminal connected to said output line of said fourth logic gate; a first output terminal connected to another input line in said plurality of input lines of said second logic gate; and a second output terminal connected to another input line in said plurality of said lines of said third logic gate; wherein said second programmable demultiplexer programmably connects said second programmable demultiplexer input terminal to one of said first and second output terminals of said second programmable demultiplexer, and programmably disconnects said second programmable demultiplexer input terminal from the other of said first and second output terminals of said second programmable demultiplexer.
Claim 14
Dependent Claim
77 words
In a programmable logic device, a structure as in claim 8 further wherein said second programmable demultiplexer further comprises a third output terminal, and said second programmable demultiplexer programmably connects said second programmable demultiplexer input terminal to one of said first, second, and third output terminals of said second programmable demultiplexer, and programmably disconnects said second programmable demultiplexer input terminal from the other two of said first, second, and third output terminals of said second programmable demultiplexer.
Claim 15
Dependent Claim
167 words
In a programmable logic device, a structure as in claim 7 further comprising: a fifth logic gate having an output line; a sixth logic gate having a plurality of input lines; and a third programmable demultiplexer having: an input terminal connected to said output line of said fifth logic gate; a first output terminal connected to yet another input line in said plurality of input lines of said second logic gate; a second output terminal connected to yet another input line in said plurality of input lines of said third logic gate; and a third output terminal connected to one input line in said plurality of input lines of said sixth logic gate wherein said third programmable demultiplexer programmably connects said third programmable demultiplexer input terminal to one of said first, second, and third output terminals of said third programmable demultiplexer, and programmably disconnects said third programmable demultiplexer input terminal from the other two of said first, second, and third output terminals of said third programmable demultiplexer.
Claim 16
Dependent Claim
27 words
In a programmable logic device, a structure as in claim 10 wherein said first and fifth logic gates are OR gates in a programmable AND-fixed OR array.
Claim 17
Dependent Claim
42 words
In a programmable logic device, a structure as in claim 10 wherein said second logic gate is in a first logic macrocell; said third logic gate is in a second logic macrocell; and sixth logic gate is in a third logic macrocell.
Claim 18
Dependent Claim
96 words
In a programmable logic device, a logic allocator comprising: a first logic gate having an output line; and a first programmable demultiplexer having: an input terminal connected to said output line of said first logic gate; a first output terminal; and a second output terminal; wherein said first programmable demultiplexer programmably connects said first programmable demultiplexer input terminal to one of said first and second output terminals of said first programmable demultiplexer, and programmably disconnects said first programmable demultiplexer input terminal from the other of said first and second output terminals of said first programmable demultiplexer.
Claim 19
Dependent Claim
96 words
In a programmable logic device, a logic allocator comprising: a first logic gate having an output line; and a first programmable demultiplexer having: an input terminal connected to said output line of said first logic gate; a first output terminal; and a second output terminal; wherein said first programmable demultiplexer programmably connects said first programmable demultiplexer input terminal to one of said first and second output terminals of said first programmable demultiplexer, and programmably disconnects said first programmable demultiplexer input terminal from the other of said first and second output terminals of said first programmable demultiplexer.
Claim 20
Dependent Claim
101 words
In a programmable logic device, a logic allocator as in claim 13 further comprising: a second logic gate having an output line; and a second programmable demultiplexer having: an input terminal connected to said output line of said second logic gate; a first output terminal; and a second output terminal; wherein said second programmable demultiplexer programmably connects said second programmable demultiplexer input terminal to one of said first and second output terminals of said second programmable demultiplexer, and programmably disconnects said second programmable demultiplexer input terminal from the other of said first and second output terminals of said second programmable demultiplexer.
Claim 21
Dependent Claim
77 words
In a programmable logic device, a structure as in claim 14 further wherein said second programmable demultiplexer further comprises a third output terminal, and said second programmable demultiplexer programmably connects said second programmable demultiplexer input terminal to one of said first, second, and third output terminals of said second programmable demultiplexer, and programmably disconnects said second programmable demultiplexer input terminal from the other two of said first, second, and third output terminals of said second programmable demultiplexer.
Claim 22
Dependent Claim
107 words
In a programmable logic device, a structure as in claim 13 further comprising: a second logic gate having an output line; and a second programmable demultiplexer having: an input terminal connected to said output line of said second logic gate; a first output terminal; a second output terminal; and a third output terminal; wherein said second programmable demultiplexer programmably connects said second programmable demultiplexer input terminal to one of said first, second, and third output terminals of said second programmable demultiplexer, and programmably disconnects said second programmable demultiplexer input terminal from the other two of said first, second, and third output terminals of said second programmable demultiplexer.
Claim 23
Dependent Claim
27 words
In a programmable logic device, a structure as in claim 16 wherein said first and second logic gates are OR gates in a programmable AND-fixed OR array.
Claim 24
Dependent Claim
139 words
In a programmable logic device, a structure comprising: a plurality of logic gates wherein each logic gate in said plurality of logic gates has an output line; a plurality of logic macrocells wherein each logic macrocell has a plurality of input lines; and a plurality of programmable demultiplexers wherein each demultiplexer has an input terminal and a plurality of output terminals, and each programmable demultiplexer programmably connects said programmable demultiplexer input terminal to one of said plurality of output terminals of said programmable demultiplexer, and programmably disconnects said programmable demultiplexer input terminal from all others of said plurality of output terminals of said programmable demultiplexer; wherein each programmable demultiplexer input terminal is connected to a different logic gate output line; and each input line of a logic macrocell is connected to an output terminal of a different programmable demultiplexer.
Claim 25
Dependent Claim
139 words
In a programmable logic device, a structure comprising: a plurality of logic gates wherein each logic gate in said plurality of logic gates has an output line; a plurality of logic macrocells wherein each logic macrocell has a plurality of input lines; and a plurality of programmable demultiplexers wherein each demultiplexer has an input terminal and a plurality of output terminals, and each programmable demultiplexer programmably connects said programmable demultiplexer input terminal to one of said plurality of output terminals of said programmable demultiplexer, and programmably disconnects said programmable demultiplexer input terminal from all others of said plurality of output terminals of said programmable demultiplexer; wherein each programmable demultiplexer input terminal is connected to a different logic gate output line; and each input line of a logic macrocell is connected to an output terminal of a different programmable demultiplexer.
Claim 26
Dependent Claim
38 words
In a programmable logic device, a structure as in claim 18 wherein the plurality of input lines of each macrocell comprises N input lines; and the plurality of output terminals of each programmable demultiplexer comprises N output terminals.
Claim 27
Dependent Claim
26 words
In a programmable logic device consisting of, a structure as in claim 19 wherein N is selected from the group consisting of two, three, and four.
Claim 28
Dependent Claim
35 words
In a programmable logic device, a structure as in claim 18 wherein each logic gate in said plurality of logic gates is connected to a different group of product terms in a product term array.
Claim 29
Dependent Claim
153 words
In a programmable logic device, a structure comprising: a plurality of first logic gates wherein each first logic gate in said plurality of first logic gates has an output line; a plurality of second logic gates wherein each second logic gate in said plurality of second logic gates has a plurality of input lines; and a plurality of programmable demultiplexers wherein each demultiplexer has an input terminal and a plurality of output terminals, and each programmable demultiplexer programmably connects said programmable demultiplexer input terminal to one of said plurality of output terminals of said programmable demultiplexer, and programmably disconnects said programmable demultiplexer input terminal from all others of said plurality of output terminals of said programmable demultiplexer; wherein each programmable demultiplexer input terminal is connected to a different first logic gate output line; and each input line of a second logic gate is connected to an output terminal of a different programmable demultiplexer.
Claim 30
Dependent Claim
153 words
In a programmable logic device, a structure comprising: a plurality of first logic gates wherein each first logic gate in said plurality of first logic gates has an output line; a plurality of second logic gates wherein each second logic gate in said plurality of second logic gates has a plurality of input lines; and a plurality of programmable demultiplexers wherein each demultiplexer has an input terminal and a plurality of output terminals, and each programmable demultiplexer programmably connects said programmable demultiplexer input terminal to one of said plurality of output terminals of said programmable demultiplexer, and programmably disconnects said programmable demultiplexer input terminal from all others of said plurality of output terminals of said programmable demultiplexer; wherein each programmable demultiplexer input terminal is connected to a different first logic gate output line; and each input line of a second logic gate is connected to an output terminal of a different programmable demultiplexer.
Claim 31
Dependent Claim
40 words
In a programmable logic device, a structure as in claim 22 wherein the plurality of input lines of each second logic gate comprises N input lines; and the plurality of output terminals of each programmable demultiplexer comprises N output terminals.
Claim 32
Dependent Claim
24 words
In a programmable logic device, a structure as in claim 23 wherein N is selected from the group consisting of two, three, and four.
Claim 33
Dependent Claim
37 words
In a programmable logic device, a structure as in claim 23 wherein each first logic gate in said plurality of first logic gates is connected to a different group of product terms in a product term array.
Claim 34
Dependent Claim
20 words
In a programmable logic device, a structure as in claim 22 wherein said first logic gate is an OR gate.
Claim 35
Dependent Claim
20 words
In a programmable logic device, a structure as in claim 22 wherein said second logic gate is an OR gate.
Claim 36
Dependent Claim
104 words
In a programmable logic device having a programmable array with a plurality of output lines, a logic allocator comprising: a programmable router element coupled to a set of output lines of said programmable array so that signals on said output lines of said programmable array are input signals to said router element, and having a multiplicity of output terminals wherein upon programming said programmable router element, said input signals are connected to one output terminal in said multiplicity of output terminals of said programmable router element and disconnected from all other output terminals in said multiplicity of output terminals of said programmable router element.
Claim 37
Dependent Claim
104 words
In a programmable logic device having a programmable array with a plurality of output lines, a logic allocator comprising: a programmable router element coupled to a set of output lines of said programmable array so that signals on said output lines of said programmable array are input signals to said router element, and having a multiplicity of output terminals wherein upon programming said programmable router element, said input signals are connected to one output terminal in said multiplicity of output terminals of said programmable router element and disconnected from all other output terminals in said multiplicity of output terminals of said programmable router element.
Claim 38
Dependent Claim
136 words
In a programmable logic device having a programmable array with a plurality of output lines, a logic allocator as in claim 28 wherein said router element further comprises: a logic gate having an output line and a plurality of input terminals wherein each input terminal of said logic gate is connected to a different output line in said set of programmable array output lines; and a programmable demultiplexer having: an input terminal connected to said output line of said logic gate; a first output terminal; and a second output terminal; wherein said programmable demultiplexer programmably connects said programmable demultiplexer input terminal to one of said first and second output terminals of said programmable demultiplexer, and programmably disconnects said programmable demultiplexer input terminal from the other of said first and second output terminals of said programmable demultiplexer.
Claim 39
Dependent Claim
142 words
In a programmable logic device having a programmable array with a plurality of output lines, a logic allocator as in claim 28 wherein said router element further comprises: a logic gate having an output line and a plurality of input terminals wherein each input terminal of said logic gate is connected to a different output line in said set of programmable array output lines; a programmable demultiplexer having: an input terminal connected to said output line of said logic gate; a first output terminal; and a second output terminal; a third output terminal; wherein said programmable demultiplexer programmably connects said programmable demultiplexer input terminal to one of said first, second, and third output terminals of said programmable demultiplexer, and programmably disconnects said programmable demultiplexer input terminal from the other two of said first, second, and third output terminals of said programmable demultiplexer.
Claim 40
Dependent Claim
147 words
In a programmable logic device having a programmable array with a plurality of output lines, a logic allocator as in claim 28 wherein said router element further comprises: a logic gate having an output line and a plurality of input terminals wherein each input terminal of said logic gate is connected to a different output line in said set of programmable array output lines; a programmable demultiplexer having: an input terminal connected to said output line of said logic gate; a first output terminal; and a second output terminal; a third output terminal; a fourth output terminal; wherein said programmable demultiplexer programmably connects said programmable demultiplexer input terminal to one of said first, second, third, fourth output terminals of said programmable demultiplexer, and programmably disconnects said programmable demultiplexer input terminal from the other three of said first, second, third, and fourth output terminals of said programmable demultiplexer.
References Cited (Backward Citations)
US4366393A
Cited
US4742252A
Cited
US4931671A
Cited
US4963768A
Cited
US5015884A
Cited
US5225719A
Cited
US4758746A
Cited
US4779229A
Cited
US4878200A
Cited
US5136188A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |