Patent US5485035A successfully refreshed from Google Patents.
US5485035A
Expired / Lapsed
US
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Method for planarization of an integrated circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1993-12-28
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Granted: 1996-01-16
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Expires: 2013-12-28
Abstract
Abstract A method for planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer.
Inventors
- 👤 Yih-Shung Lin
- 👤 Kuei-Wu Huang
- 👤 Lun-Tseng Lu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:03
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
197 words
A structure in an integrated circuit, comprising: a first conductive layer defining an interconnect layer; a first insulating layer overlying the integrated circuit, wherein an upper surface of the first insulating layer is non-planar and contains lower topographical regions; a plurality of planarizing material regions on the first insulating layer, wherein the planarizing material regions fill in the lower topographical regions thereof to form a substantially planar upper surface, wherein no planarizing material regions lie above a selected portion of the first conductive layer; a layer of insulating material overlying the first insulating layer and the planarizing material regions; an opening through the layer of insulating material and the first insulating layer exposing the selected portion of the first conductive layer; and a second conductive layer overlying portions of the layer of insulating material and extending into the opening to make electrical contact with the first conductive layer, wherein the layer of insulating material is a multi layer comprising: a second insulating layer overlying the integrated circuit; and a third insulating layer overlying the second insulating layer, wherein the third insulating layer is formed from a material which can be selectively etched over the second insulating layer.
Claim 2
Dependent Claim
197 words
A structure in an integrated circuit, comprising: a first conductive layer defining an interconnect layer; a first insulating layer overlying the integrated circuit, wherein an upper surface of the first insulating layer is non-planar and contains lower topographical regions; a plurality of planarizing material regions on the first insulating layer, wherein the planarizing material regions fill in the lower topographical regions thereof to form a substantially planar upper surface, wherein no planarizing material regions lie above a selected portion of the first conductive layer; a layer of insulating material overlying the first insulating layer and the planarizing material regions; an opening through the layer of insulating material and the first insulating layer exposing the selected portion of the first conductive layer; and a second conductive layer overlying portions of the layer of insulating material and extending into the opening to make electrical contact with the first conductive layer, wherein the layer of insulating material is a multi layer comprising: a second insulating layer overlying the integrated circuit; and a third insulating layer overlying the second insulating layer, wherein the third insulating layer is formed from a material which can be selectively etched over the second insulating layer.
Claim 3
Dependent Claim
16 words
The structure of claim 1, wherein the second insulating layer is made of boron doped oxide.
Claim 4
Dependent Claim
15 words
The structure of claim 1, wherein the third insulating layer is made of undoped oxide.
Claim 5
Dependent Claim
15 words
The structure of claim 1, wherein the second conductive layer is made of a metal.
Claim 6
Dependent Claim
222 words
A structure in an integrated circuit, comprising: a first conductive layer defining an interconnect layer; a first insulating layer overlying the integrated circuit, wherein the surface of the first insulating layer has lower and higher topographical regions, and wherein planarizing material regions fill in the lower topographical regions of the first insulating layer so that an upper surface of the first insulating layer is substantially coplanar with upper surfaces of the planarizing material regions, wherein the first insulating layer upper surface and the planarizing material region upper surfaces form a substantially planar surface, and wherein no planarizing material regions lie above a selected portion of the first conductive layer; a layer of insulating material overlying the first insulating layer and the planarizing material regions; an opening through the layer of insulating material and the first insulating layer exposing the selected portion of the first conductive layer; and a second conductive layer overlying portions of the layer of insulating material and extending into the opening to make electrical contact with the first conductive layer, wherein the layer of insulating material is a multi-layer, comprising: a second insulating layer overlying the first insulating layer; and a third insulating layer overlying the second insulating layer, wherein the third insulating layer is formed from a material which can be selectively etched over the second insulating layer.
Claim 7
Dependent Claim
222 words
A structure in an integrated circuit, comprising: a first conductive layer defining an interconnect layer; a first insulating layer overlying the integrated circuit, wherein the surface of the first insulating layer has lower and higher topographical regions, and wherein planarizing material regions fill in the lower topographical regions of the first insulating layer so that an upper surface of the first insulating layer is substantially coplanar with upper surfaces of the planarizing material regions, wherein the first insulating layer upper surface and the planarizing material region upper surfaces form a substantially planar surface, and wherein no planarizing material regions lie above a selected portion of the first conductive layer; a layer of insulating material overlying the first insulating layer and the planarizing material regions; an opening through the layer of insulating material and the first insulating layer exposing the selected portion of the first conductive layer; and a second conductive layer overlying portions of the layer of insulating material and extending into the opening to make electrical contact with the first conductive layer, wherein the layer of insulating material is a multi-layer, comprising: a second insulating layer overlying the first insulating layer; and a third insulating layer overlying the second insulating layer, wherein the third insulating layer is formed from a material which can be selectively etched over the second insulating layer.
Claim 8
Dependent Claim
16 words
The structure of claim 5, wherein the second insulating layer is made of boron doped oxide.
Claim 9
Dependent Claim
15 words
The structure of claim 5, wherein the third insulating layer is made of undoped oxide.
Claim 10
Dependent Claim
30 words
The structure of claim 1, wherein the opening extends vertically through the first and second insulating layers, and wherein the opening has rounded upper corners within the third insulating layer.
Claim 11
Dependent Claim
30 words
The structure of claim 5, wherein the opening extends vertically through the first and second insulating layers, and wherein the opening has rounded upper corners within the third insulating layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |