Patent US5483644A successfully refreshed from Google Patents.
US5483644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for increasing cacheable address space in a second level cache
Assignee: Callahan Cellular LLC
•
Filing: 1993-04-15
•
Granted: 1996-01-09
•
Expires: 2013-04-15
Abstract
Abstract A Tag Field for a second level cache memory subsystem in a PC is provided which replaces the fixed Valid and Dirty bits with programmable bits which can each be programmed as a Valid bit, a Dirty bit, or an additional address bit. The cacheable address space of the PC can thus be increased by programming one or more of the two programmable bits as additional address bits. This method can be implemented on existing computers by modifying the system or application software to utilize these programmable bits in a manner to achieve more optimum performance of the cache.
Inventors
- 👤 Nicholas J. Richardson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:38
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0804; G06F12/0897
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
90 words
A method for increasing the address range of a cache system having a cache memory comprised of a plurality of cache entries, said method comprising the steps of: providing a plurality of cache tag field memory locations corresponding to each cache entry, each cache tag field memory location having a plurality of bits comprising address bits and at least one programmable bit; storing a portion of address data in said address bits; and programming said programmable bit with another portion of said address data to provide an additional address bit.
Claim 2
Independent Claim
90 words
A method for increasing the address range of a cache system having a cache memory comprised of a plurality of cache entries, said method comprising the steps of: providing a plurality of cache tag field memory locations corresponding to each cache entry, each cache tag field memory location having a plurality of bits comprising address bits and at least one programmable bit; storing a portion of address data in said address bits; and programming said programmable bit with another portion of said address data to provide an additional address bit.
Claim 3
Independent Claim
98 words
A method for increasing the address range of a cache system having a cache memory comprised of a plurality of cache entries, said method comprising the steps of: providing a plurality of cache tag field memory locations corresponding to each cache entry, each cache tag field memory location having a plurality of bits comprising address bits and status bits; replacing said status bits with programmable bits; storing a portion of address data in said address bits; and programming at least one of said programmable bits with another portion of said address data to provide an additional address bit.
Claim 4
Independent Claim
98 words
A method for increasing the address range of a cache system having a cache memory comprised of a plurality of cache entries, said method comprising the steps of: providing a plurality of cache tag field memory locations corresponding to each cache entry, each cache tag field memory location having a plurality of bits comprising address bits and status bits; replacing said status bits with programmable bits; storing a portion of address data in said address bits; and programming at least one of said programmable bits with another portion of said address data to provide an additional address bit.
Claim 5
Dependent Claim
39 words
The method of claim 2 wherein said step of programming at least one of said programmable bits comprises the step of programming all of said programmable bits with another portion of said address data to provide additional address bits.
References Cited (Backward Citations)
US4395754A
Cited
US4763250A
Cited
US4947319A
Cited
US5133058A
Cited
US5276832A
Cited
US5132927A
Cited
US5222222A
Cited
US5287481A
Cited
US5337477A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |