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US5482887A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device with a passivated side

Assignee: NXP BV
•
Filing: 1993-12-22
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Granted: 1996-01-09
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Expires: 2013-12-22
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Abstract

Abstract A method of manufacturing semiconductor devices with a passivated semiconductor body (1) provided with an electrode (2) and fastened on an electrically conducting support body (3), in which method a slice of semiconductor material (5) is fastened on a surface (6) of an electrically conducting auxiliary slice (7), and mesa structures (8) are formed in the slice of semiconductor material (5) by the application of grooves (9) in the slice of semiconductor material (5) subsequently, a layer of insulating material (10) is provided on the walls of the grooves (9), electrodes (2) are provided on upper sides (11) of the mesa structures (8), and the auxiliary slice (7) with the mesa structures (8) is split up at the areas of the grooves (9) into individual semiconductor bodies (1) each fastened on its own support body (3). According to the invention, the electrodes (2) are provided in that an electrically conducting layer (25) is deposited both on the upper side (11) of the mesa structures (8) and on the layer of insulating material (10) and, during splitting-up of the auxiliary slice (7) with mesa structures (8), this layer (25) is also split up into separate electrodes (2) which lie on the upper side (11) of a mesa structure (8) as well as on the layer of insulating material (10). The method according to the invention is simpler than a known method. Moreover, semiconductor devices are made by the method according to the invention which have a better resistance to higher voltages because the electrodes (2) also extend over the insulating material (10).

Inventors

  • 👤 Geert J. Duinkerken
  • 👤 Roelvinus M. M. Fonville

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 08:25
CPC Classifications
H; H10; H10P; H10P50/00; H10P54/00; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S438/00; Y10S438/958

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 167 words
A method of manufacturing semiconductor devices each having a passivated semiconductor body provided with an electrode and fastened on an electrically conducting support body, in which a slice of semiconductor material is fastened on a surface of an electrically conducting auxiliary slice and mesa structures are formed in the slice of semiconductor material by forming grooves in the slice of semiconductor material, after which a layer of insulating material is provided on the walls of the grooves, an electrically conducting layer is applied over the entire resulting structure of the slice of semiconductor material comprising mesa structures and grooves, the auxiliary slice comprising the mesa structures is then split up at the areas of the insulated grooves into separate semiconductor bodies each fastened on its own support body, and this electrically conducting layer is split up into separate electrodes, which lie both on the upper side of a mesa structure and on the layer of insulating material, during splitting-up of the auxiliary slice comprising the mesa structures.
Claim 2
Independent Claim 167 words
A method of manufacturing semiconductor devices each having a passivated semiconductor body provided with an electrode and fastened on an electrically conducting support body, in which a slice of semiconductor material is fastened on a surface of an electrically conducting auxiliary slice and mesa structures are formed in the slice of semiconductor material by forming grooves in the slice of semiconductor material, after which a layer of insulating material is provided on the walls of the grooves, an electrically conducting layer is applied over the entire resulting structure of the slice of semiconductor material comprising mesa structures and grooves, the auxiliary slice comprising the mesa structures is then split up at the areas of the insulated grooves into separate semiconductor bodies each fastened on its own support body, and this electrically conducting layer is split up into separate electrodes, which lie both on the upper side of a mesa structure and on the layer of insulating material, during splitting-up of the auxiliary slice comprising the mesa structures.
Claim 3
Dependent Claim 44 words
A method as claimed in claim 1, characterized in that grooves are provided to a width and splitting-up takes place by sawing through the auxiliary slice comprising mesa structures, the width of the grooves being greater than that of a sawcut used during sawing.
Claim 4
Dependent Claim 41 words
A method as claimed in claim 2, characterized in that the layer of insulating material is provided to such a thickness at the area of the sawcut that the layer of insulating material is thicker there than the electrically conducting layer.
Claim 5
Dependent Claim 30 words
A method as claimed in claim 3, characterized in that the layer of insulating material is provided to such a thickness that the grooves are substantially filled with insulating material.
Claim 6
Dependent Claim 35 words
A method as claimed in claim 2, characterized in that the semiconductor body with support body is given a plane sawcut surface during sawing-through which is suitable as a mounting surface for the semiconductor device.
Claim 7
Dependent Claim 36 words
A method as claimed in claim 5, characterized in that a slice of semiconductor material is used as the auxiliary slice which has such a thickness that a surface mounted device of standard dimensions is obtained.
Claim 8
Dependent Claim 28 words
A method as claimed claim 1, characterized in that the grooves are provided through removal of material from the slice of semiconductor material by bombardment with abrasive particles.
Claim 9
Dependent Claim 39 words
A method as claimed in claim 1, characterized in that the layer of insulating material is provided by filling the grooves with a glass dispersion and by subsequently subjecting the auxiliary slice comprising mesa structures to a heat treatment.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-01-08 1999-07-10 2000-01-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-01-08 2003-07-10 2004-01-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-01-08 2007-07-10 2008-01-09 $7700.00 Window Closed / Lapsed

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