System and method for error detection and reducing simultaneous switching noise

Claim 1

A system for providing a net signalling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least one error detection bit, the system comprising an encoder that encodes an R bit input word to an S bit output word, the encoder encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the R bit input word and at least one error detection bit for each byte of the R bit input word, the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number, and N an even number >M.

Claim 2

A system for providing a net signalling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least one error detection bit, the system comprising an encoder that encodes an R bit input word to an S bit output word, the encoder encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the R bit input word and at least one error detection bit for each byte of the R bit input word, the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number, and N an even number >M.

Claim 7

A system for providing a net signalling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least two error detection bits, the system comprising an encoder that encodes an R bit input word to an S bit output word, the encoder encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the R bit input word and at least two error detection bits for each byte of the R bit input word, the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number, and N an even number >M.

Claim 8

A system for providing a net signalling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least two error detection bits, the system comprising an encoder that encodes an R bit input word to an S bit output word, the encoder encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the R bit input word and at least two error detection bits for each byte of the R bit input word, the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number, and N an even number >M.

Claim 15

A system for providing a net signalling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least one error detection bit, the system comprising: an encoder that encodes an R bit input word to an S bit output word, the encoder encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the R bit input word and at least one error detection bit for each byte of the R bit input word, the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number, and N an even number M; and a receiver that receives words encoded by an encoder and counts the binary "1" values and the binary "0" values in the received encoded words to determine if any of said encoded words contain data transmission errors.

Claim 16

A system for providing a net signalling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least one error detection bit, the system comprising: an encoder that encodes an R bit input word to an S bit output word, the encoder encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the R bit input word and at least one error detection bit for each byte of the R bit input word, the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number, and N an even number M; and a receiver that receives words encoded by an encoder and counts the binary "1" values and the binary "0" values in the received encoded words to determine if any of said encoded words contain data transmission errors.

Claim 21

A system for providing a net signalling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least two error detection bits, the system comprising: an encoder that encodes an R bit input word to an S bit output word, the encoder encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the R bit input word and at least two error detection bits for each byte of the R bit input word, the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number, and N an even number M; and a receiver that receives words encoded by an encoder and counts the binary "1" values and the binary "0" values in the received encoded words to determine if any of said encoded words contain data transmission errors.

Claim 22

A system for providing a net signalling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least two error detection bits, the system comprising: an encoder that encodes an R bit input word to an S bit output word, the encoder encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the R bit input word and at least two error detection bits for each byte of the R bit input word, the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number, and N an even number M; and a receiver that receives words encoded by an encoder and counts the binary "1" values and the binary "0" values in the received encoded words to determine if any of said encoded words contain data transmission errors.

Claim 29

A method for providing a net signaling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least one error detection bit, the method comprising encoding an R bit input, word to an S bit output word by encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, with each combination of the M number of binary bits being encoded according to one combination of N encode binary bits, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the the R bit input word and at least one error detection bit for each byte of the R bit input word, and the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number >1, and N an even number >M.

Claim 30

A method for providing a net signaling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least one error detection bit, the method comprising encoding an R bit input, word to an S bit output word by encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, with each combination of the M number of binary bits being encoded according to one combination of N encode binary bits, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the the R bit input word and at least one error detection bit for each byte of the R bit input word, and the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number >1, and N an even number >M.

Claim 35

A method for providing a net signaling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least two error detection bits, the method comprising encoding an R bit input word to an S bit output word by encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, with each combination of the M number of binary bits being encoded according to one combination of N encode binary bits, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the the R bit input word and at least two error detection bits for each byte of the R bit input word, and the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number >1, and N an even number >M.

Claim 36

A method for providing a net signaling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least two error detection bits, the method comprising encoding an R bit input word to an S bit output word by encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, with each combination of the M number of binary bits being encoded according to one combination of N encode binary bits, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the the R bit input word and at least two error detection bits for each byte of the R bit input word, and the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number >1, and N an even number >M.

Claim 43

A method for providing a net signaling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least one error detection bit, the method comprising the steps of: (a) encoding an R bit input word to an S bit output word by encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output work, with each combination of the M number of binary bits being encoded according to one combination of N encode binary bits, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the the R bit input word and at least one error detection bit for each byte of the R bit input word, and the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number >1, and N an even number >M; and (b) receiving words encoded according to step (a) and, counting the binary "1" values and the binary "0" values in the received encoded words for determining if there are data transmission errors in said received encoded words.

Claim 44

A method for providing a net signaling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least one error detection bit, the method comprising the steps of: (a) encoding an R bit input word to an S bit output word by encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output work, with each combination of the M number of binary bits being encoded according to one combination of N encode binary bits, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the the R bit input word and at least one error detection bit for each byte of the R bit input word, and the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number >1, and N an even number >M; and (b) receiving words encoded according to step (a) and, counting the binary "1" values and the binary "0" values in the received encoded words for determining if there are data transmission errors in said received encoded words.

Claim 49

A method for providing a net signaling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least two error detection bits, the method comprising the-steps of: (a) encoding an R bit input word to an S bit output word by encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, with each combination of the M number of binary bits being encoded according to one combination of N encode binary bits, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the the R bit input word and at least two error detection bits for each byte of the R bit input word, and the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number >1, and N an even number >M; and (b) receiving words encoded according to step (a) and, counting the binary "1" values and the binary "0" values in the received encoded words for determining if there are data transmission errors in said received encoded words.

Claim 50

A method for providing a net signaling current of substantially zero at each cycle time for reducing a noise level for simultaneous switching outputs of an integrated circuit chip and generating a signal having at least two error detection bits, the method comprising the-steps of: (a) encoding an R bit input word to an S bit output word by encoding each of P groupings of M number of binary bits of the R bit input word to an even number of N encode binary bits to form the S bit output word, with each combination of the M number of binary bits being encoded according to one combination of N encode binary bits, the M number of binary bits being selected such that one P grouping of M number of binary bits includes binary bits of the the R bit input word and at least two error detection bits for each byte of the R bit input word, and the combinations of N encode binary bits including an equal number of binary "1" values and binary "0" values, with P>0, M>0, R>0, N an even number >1, and N an even number >M; and (b) receiving words encoded according to step (a) and, counting the binary "1" values and the binary "0" values in the received encoded words for determining if there are data transmission errors in said received encoded words.