US3902117A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pcm error detection
Assignee: International Standard Electric Corp
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Filing: 1974-01-24
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Granted: 1975-08-26
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Expires: 1994-01-24
Abstract
Abstract The error detection arrangement operates on a special code produced by converting a 4 bit binary code word into either of two 3 bit ternary words of opposite polarity disparity values so as to reduce to a minimum the accumulated disparity of the ternary words transmitted. The arrangement derives at the conclusion of each ternary word the polarity of the accumulated disparity. This polarity is stored in a temporary store. In addition, the polarity of the disparity is derived at the conclusion of each ternary word. Logic circuitry determines when the polarity of the disparity for a word is the same as the accumulated disparity at the conclusion of the previous word and produces an error output when the two polarities are the same. When an error output is produced, the information in the temporary store is corrected.
Inventors
- 👤 David Sheppard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:48
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4923; H04L25/4925
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
232 words
An error detection arrangement for a receive translator employed in a PCM system in which, for transmission, digital words having one word disparity polarity are transmitted when the accumulated disparity of a transmitted code signal is of the opposite polarity, and vice versa, said arrangement comprising first means for deriving at the conclusion of each digital word in said transmitted signal the polarity of the accumulated disparity of said transmitted signal; second means coupled to the output of said first means for temporarily storing the polarity of the accumulated disparity derived in said first means; third means coupled to the output of said first means for providing at the conclusion of each digital word in said transmitted signal the polarity of the word disparity of that word; and logic means coupled to said first means, said second means and said third means, said logic means being responsive to the output of said first and third means to detect when the polarity of the disparity for a digital word is the same as the polarity of the accumulated disparity for said transmitted signal at the conclusion of the previous digital word, to generate an error output signal when the two polarities are detected to be the same and to couple said error output signal to said second means to correct the information in said second means when said error output signal is generated.
Claim 2
Dependent Claim
232 words
An error detection arrangement for a receive translator employed in a PCM system in which, for transmission, digital words having one word disparity polarity are transmitted when the accumulated disparity of a transmitted code signal is of the opposite polarity, and vice versa, said arrangement comprising first means for deriving at the conclusion of each digital word in said transmitted signal the polarity of the accumulated disparity of said transmitted signal; second means coupled to the output of said first means for temporarily storing the polarity of the accumulated disparity derived in said first means; third means coupled to the output of said first means for providing at the conclusion of each digital word in said transmitted signal the polarity of the word disparity of that word; and logic means coupled to said first means, said second means and said third means, said logic means being responsive to the output of said first and third means to detect when the polarity of the disparity for a digital word is the same as the polarity of the accumulated disparity for said transmitted signal at the conclusion of the previous digital word, to generate an error output signal when the two polarities are detected to be the same and to couple said error output signal to said second means to correct the information in said second means when said error output signal is generated.
Claim 3
Dependent Claim
62 words
An arrangement according to claim 1, wherein the word disparity and the accumulated disparity characteristics of said transmitted code signal are each represented in said arrangement by a three bit binary coded word having a most significant bit indicating polarity of the disparity and the remainder of the bits is a representation of the numerical value of the amplitude of the disparity.
Claim 4
Dependent Claim
77 words
An arrangement according to claim 2, wherein said logic means includes first logic gating means coupled to said second means and said third means responsive to each bit of the 3 bit word representing the word disparity and the most significant bit of the 3 bit word representing the accumulated disparity to detect when the polarity of the word disparity is the same as the polarity of the accumulated disparity at the conclusion of the previous word.
Claim 5
Dependent Claim
39 words
An arrangement according to claim 3, wherein said logic means further includes second logic gating means coupled to said first logic gating means responsive to the outputs from said first logic gating means to generate said error output signal.
Claim 6
Dependent Claim
105 words
An arrangement according to claim 4, wherein said first means includes a binary arithmetic logic unit coupled to said second means, said third means and said first logic gating means to perform arithmetic addition operations, under control of the output signals of said first logic gating means, on the 3 bit word representing the present word disparity and the 3 bit word representing the accumulated disparity at the conclusion of the previous word to produce the accumulated disparity at the conclusion of the present word and to correct the accumulated disparity at the conclusion of the present word when said error output signal is generated.
Claim 7
Dependent Claim
105 words
An arrangement according to claim 3, wherein said first means includes a binary arithmetic logic unit coupled to said second means, said third means and said first logic gating means to perform arithmetic addition operations, under control of the output signals of said first logic gating means, on the 3 bit word representing the present word disparity and the 3 bit word representing the accumulated disparity at the conclusion of the previous word to produce the accumulated disparity at the conclusion of the present word and to correct the accumulated disparity at the conclusion of the present word when said error output signal is generated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-25 | 1979-02-24 | 1979-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-25 | 1983-02-24 | 1983-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-25 | 1987-02-24 | 1987-08-26 | $7700.00 | Window Closed / Lapsed |