US3568149A
Expired / Lapsed
US
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Digital code receiving system
Assignee: SPX Technologies Inc
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Filing: 1968-10-15
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Granted: 1971-03-02
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Expires: 1988-10-15
Abstract
Abstract A digital code receiving system is provided wherein received bits of a digital code are applied as serial inputs to a shift register, and parallel readout of the shift register is applied to a plurality of decoders, each decoder being adapted to recognize only a single code distinctive of that decoder. For code checking purposes, only codes having the same numbers of mark and space characters are used. Each decoder has first and second outputs delivered successively, the first output checks the proper elements of the code. This output then complements the shift register at an intermediate point in the bit period, and the same decoder delivers a second output if the register is fully complemented. A control device is rendered operable in response to the alternate first and second outputs of its associated decoder.
Inventors
- 👤 Henry C Sibley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:42
CPC Classifications
B; B61; B61L; B61L3/00; B61L3/16; B61L3/22; B61L3/24; B61L3/246; G; G08; G08C; G08C19/00; G08C19/16; G08C19/28; G08C25/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
137 words
A digital code receiving system for receiving selected codes having the same numbers of each of two binary characters communicated over a communication channel and applied as inputs to a shift register wherein the improvement comprises: a. decoders for delivering outputs in response to respective distinctive parallel output codes of the shift register; 1. each of the decoders having first means responsive to parallel outputs of the shift register of a distinctive code for delivering a first decoder output for complementing the shift register; 2. each of the decoders having second means responsive to parallel outputs of the shift register of the complement of the distinctive code for delivering a second output; and b. control means comprising devices associated with the severAl decoders operated in response jointly to the first and second outputs of the associated decoder.
Claim 2
Dependent Claim
137 words
A digital code receiving system for receiving selected codes having the same numbers of each of two binary characters communicated over a communication channel and applied as inputs to a shift register wherein the improvement comprises: a. decoders for delivering outputs in response to respective distinctive parallel output codes of the shift register; 1. each of the decoders having first means responsive to parallel outputs of the shift register of a distinctive code for delivering a first decoder output for complementing the shift register; 2. each of the decoders having second means responsive to parallel outputs of the shift register of the complement of the distinctive code for delivering a second output; and b. control means comprising devices associated with the severAl decoders operated in response jointly to the first and second outputs of the associated decoder.
Claim 3
Dependent Claim
52 words
each of the decoders having second means responsive to parallel outputs of the shift register of the complement of the distinctive code for delivering a second output; and b. control means comprising devices associated with the severAl decoders operated in response jointly to the first and second outputs of the associated decoder.
Claim 4
Dependent Claim
52 words
each of the decoders having second means responsive to parallel outputs of the shift register of the complement of the distinctive code for delivering a second output; and b. control means comprising devices associated with the severAl decoders operated in response jointly to the first and second outputs of the associated decoder.
Claim 5
Dependent Claim
66 words
The invention according to claim 1 wherein each of the decoders comprises a first plurality of gates having their inputs controlled by the parallel outputs of the shift register, some of the gates being effective to deliver outputs upon detection of said distinctive code in the register and others of the gates being effective to deliver outputs upon detection of the complement of said distinctive code.
Claim 6
Dependent Claim
52 words
The invention according to claim 2 wherein each of the gates is a four input AND gate delivering an output only provided that inputs from two stages of the shift register are of a particular character and inputs from two other stages of the shift register are not of said particular character.
Claim 7
Dependent Claim
66 words
The invention according to claim 3 wherein each of the decoders comprises a second plurality of gates having their inputs controlled by outputs of the first plurality of gates and effective to deliver output pulses alternately at times when the distinctive code is detected by the first plurality of gates and when the complement of the distinctive code is detected by the first plurality of gates.
Claim 8
Dependent Claim
66 words
The invention according to claim 4 wherein each of the gates of the second plurality of gates is a four input AND gate delivering an output only when two of its inputs are from respective ones of said first plurality of gates and are of a particular character, and inputs from two other ones of said first plurality of gates are not of said particular character.
Claim 9
Dependent Claim
44 words
The invention according to claim 1 wherein the first and second outputs of the decoder are produced alternately and means is provided for maintaining the device in an actuated condition only so long as the alternate outputs are repeatedly produced by the associated decoder.
Claim 10
Dependent Claim
42 words
The invention according to claim 6 wherein the device is a relay and means is provided for alternately charging and discharging a capacitor in response to the alternate outputs of the decoder, the relay being energized by the discharging of the capacitor.
Claim 11
Independent Claim
159 words
A system for receiving selected code bits communicated sequentially over a communication channel and applied as successive bits to a shift register wherein the improvement comprises: a. decoding means having its input governed by parallel output from respective stages of the shift register and operable to deliver a first output when a particular distinctive code is applied to the input of the decoding means; b. timing means for normally shifting the register at an intermediate point in the reception of each bit; c. control means governed jointly by the first output of the decoder and by the timing means for complementing the shift register at an intermediate point in the reception of a bit prior to the normal shifting of the register during that bit; d. said decoding means being effective to generate a second output when the register is complemented; and e. means for governing a device in response to alternate first and second outputs of the decoder.
Claim 12
Independent Claim
159 words
A system for receiving selected code bits communicated sequentially over a communication channel and applied as successive bits to a shift register wherein the improvement comprises: a. decoding means having its input governed by parallel output from respective stages of the shift register and operable to deliver a first output when a particular distinctive code is applied to the input of the decoding means; b. timing means for normally shifting the register at an intermediate point in the reception of each bit; c. control means governed jointly by the first output of the decoder and by the timing means for complementing the shift register at an intermediate point in the reception of a bit prior to the normal shifting of the register during that bit; d. said decoding means being effective to generate a second output when the register is complemented; and e. means for governing a device in response to alternate first and second outputs of the decoder.
Claim 13
Dependent Claim
33 words
The invention according to claim 8 wherein the timing means comprises an oscillator and a frequency divider for determining the intermediate point in the reception of a code bit for complementing the register.
References Cited (Backward Citations)
US3199077A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |