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US5481494A
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Method for tightening VT distribution of 5 volt-only flash EEPROMS
Assignee: Cypress Semiconductor Corp
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Filing: 1994-12-22
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Granted: 1996-01-02
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Expires: 2014-12-22
Abstract
Abstract There is provided an improved method for tightening the distribution of control gate threshold voltages of erase cells in flash EEPROM devices. A relatively low positive voltage is applied to the source regions of the EEPROM devices during an entire erase cycle. The magnitude of a negative constant voltage applied to control gates of the EEPROM devices is lowered to a predetermined voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution. The value of a load resistor coupled between the low positive voltage and source regions is reduced simultaneously to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage. As a result, an improved threshold voltage V T distribution after erase is obtained without sacrificing any reduction in the erase speed.
Inventors
- 👤 Yuan Tang
- 👤 Lee E. Cleveland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:47
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3468; G11C16/3477; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
154 words
A method for tightening the distribution of control gate threshold voltages of erased cells of flash EEPROM devices, said method comprising the steps of: applying a relatively low positive voltage to source regions of said EEPROM devices during an entire erase cycle; lowering the magnitude of a negative constant voltage applied to control gates of said EEPROM devices from a predetermined higher voltage level to a predetermined lower voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution; and reducing simultaneously the value of a load resistor coupled between the low positive voltage and the source regions from a predetermined higher value to a predetermined lower value so as to compensate for an increased erase time caused by the lowering of the magnitude of the negative constant voltage, whereby an improved threshold voltage V T distribution after erase is obtained without sacrificing any reduction in the erase speed.
Claim 2
Independent Claim
154 words
A method for tightening the distribution of control gate threshold voltages of erased cells of flash EEPROM devices, said method comprising the steps of: applying a relatively low positive voltage to source regions of said EEPROM devices during an entire erase cycle; lowering the magnitude of a negative constant voltage applied to control gates of said EEPROM devices from a predetermined higher voltage level to a predetermined lower voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution; and reducing simultaneously the value of a load resistor coupled between the low positive voltage and the source regions from a predetermined higher value to a predetermined lower value so as to compensate for an increased erase time caused by the lowering of the magnitude of the negative constant voltage, whereby an improved threshold voltage V T distribution after erase is obtained without sacrificing any reduction in the erase speed.
Claim 3
Dependent Claim
18 words
A method as claimed in claim 1, wherein said low positive voltage has a magnitude of +5.0 volts.
Claim 4
Dependent Claim
27 words
A method as claimed in claim 2, wherein the predetermined lower voltage level of said negative constant voltage is not below the absolute value of 9.5 volts.
Claim 5
Dependent Claim
26 words
A method as claimed in claim 3, wherein the predetermined lower value of said load resistor is not below 56 Ω for a 1 megabit array.
Claim 6
Dependent Claim
25 words
A method as claimed in claim 2, wherein the predetermined lower voltage level of said negative constant voltage has the absolute value of 9.5 volts.
Claim 7
Dependent Claim
24 words
A method as claimed in claim 3, wherein the predetermined lower value of said load resistor is 56 Ω for a 1 megabit array.
References Cited (Backward Citations)
US5231602A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |