Method and apparatus for translation request buffer and requestor table for minimizing the number of accesses to the same address

Claim 2

An address translation mechanism supporting a plurality of address generators in a data processing system comprising: table means for storing address translation entries representing addresses to be translated, said table means, operatively coupled to said plurality of address generators, for supplying an address output when an address request from an address generator has a predetermined relationship with a translation entry; means for detecting when an address request from an address generator does not have a predetermined relationship with a translation entry in said table means; address buffer and compare means, operatively coupled to said detecting means, for determining whether there is an outstanding request for a translation of an address currently stored for translation and, if there is no such outstanding request, temporarily storing said address for translation; distribution means, operatively coupled to said address buffer and compare means, for identifying all requestors of address translations for each address stored for translation; and translation means for translating addresses temporarily stored by said address buffer and compare means, said translation means supplying translated addresses to said distribution means for distribution to each of said address generators identified as requesting translated addresses and to said table means, wherein said address buffer and compare means comprises second table means having a plurality of storage locations for storing addresses to be translated, each of said storage locations including an active bit position indicating whether an address is active for translation by said translation means, said address buffer and compare means further comprising compare means for comparing addresses in said second table means with an address requested for translation by said detecting means and for entering an address not found in said second table means.

Claim 3

The address translation mechanism recited in claim 1 wherein said distribution means includes means for deleting addresses for translation from said address buffer and compare means when a corresponding translated address is supplied to said distribution means.

Claim 4

The address translation mechanism recited in claim 1 wherein said address buffer and compare means further comprises: marking means responsive to all addresses requested to be translated by said detecting means for any of said address generators for identifying said distribution means for each of said address generators.

Claim 5

The address translation mechanism recited in claim 3 wherein said distribution means comprises third table means having storage locations having a predetermined relationship with addresses stored in said second table means for storing translated addresses from said translation means, said storage locations including bit positions assigned to each of said address generators and identified by said address buffer and compare means, and a mark bit position indicating that an address has been identified for distribution.

Claim 6

The address translation mechanism recited in claim 4 wherein said distribution means further includes means for resetting said active bit position in said second table means when a corresponding address has been translated by said translation means and for resetting said mark bit position in said third table means when a corresponding translated address has been distributed to said requestors.

Claim 9

The address translation mechanism recited in claim 2 wherein said address buffer and compare means further comprises: marking means responsive to all addresses requested to be translated by said detecting means for any of said address generators for identifying said distribution means for each of said address generators.

Claim 10

The address translation mechanism according to claim 1, further comprising: means for inhibiting an address translation of addresses in said table means when said inhibiting means is set and for allowing an address translation of addresses in said table means when said inhibiting means is not set, such that addresses not requiring translation are not read out to said address buffer and compare means for translation, a position register for holding a position of an address to be translated, inverting means coupled to said position register for updating said position of said position register for said address to be translated; wherein with an address read out of said table means in which said inhibiting means is set, said position of an address is incremented in said position register.

Claim 11

The method according to claim 6, wherein said data processing system includes an inhibiting means for inhibiting an address translation, said method further comprising the steps of: inhibiting an address translation of address translation entries when said inhibiting means is set and for allowing an address translation of said address translation entries when said inhibiting means is not set, such that addresses not requiring translation are not read out for translation, holding a position of an address to be translated; and with an address to be translated read out and said inhibiting means set, incrementing said position of an address.

Claim 12

An address translation mechanism supporting a plurality of address generators in a data processing system comprising: table means for storing address translation entries representing addresses to be translated, said table means, operatively coupled to said plurality of address generators, for supplying an address output when an address request from an address generator has a predetermined relationship with a translation entry; means for detecting when an address request from an address generator does not have a predetermined relationship with a translation entry of said translation entries in said table means; address buffer and compare means, operatively coupled to said detecting means, for determining whether there is an outstanding request for a translation of an address currently stored for translation and, if there is no such outstanding request, temporarily storing an address for translation with said translation entries; distribution means, operatively coupled to said address buffer and compare means, for identifying all requestors of address translations for said addresses stored for translation among the stored plurality of address translation entries; and translation means for translating addresses temporarily stored by said address buffer and compare means, said translation means supplying translated addresses to said distribution means for distribution to each of said address generators identified as requesting translated addresses and to said table means, means for inhibiting an address translation of addresses in said table means when said inhibiting means is set and for allowing an address translation of addresses in said table means when said inhibiting means is not set, such that addresses not requiring translation are not read out to said address buffer and compare means for translation, a position register for holding a position of an address to be translated, inverting means coupled to said position register for updating said position of said position register for an address to be translated; wherein with an address read out of said table means in which said inhibiting means is set, said position of an address is incremented in said position register wherein said address buffer and compare means comprises second table means having a plurality of storage locations for storing addresses to be translated, each of said storage locations including an active bit position indicating whether an address is active for translation by said translation means, said address buffer and compare means further comprising compare means for comparing addresses in said second table means with an address requested for translation by said detecting means and for entering an address not found in said second table means.

Claim 13

An address translation mechanism supporting a plurality of address generators in a data processing system comprising: table means for storing address translation entries representing addresses to be translated, said table means, operatively coupled to said plurality of address generators, for supplying an address output when an address request from an address generator has a predetermined relationship with a translation entry; means for detecting when an address request from an address generator does not have a predetermined relationship with a translation entry of said translation entries in said table means; address buffer and compare means, operatively coupled to said detecting means, for determining whether there is an outstanding request for a translation of an address currently stored for translation and, if there is no such outstanding request, temporarily storing an address for translation with said translation entries; distribution means, operatively coupled to said address buffer and compare means, for identifying all requestors of address translations for said addresses stored for translation among the stored plurality of address translation entries; and translation means for translating addresses temporarily stored by said address buffer and compare means, said translation means supplying translated addresses to said distribution means for distribution to each of said address generators identified as requesting translated addresses and to said table means, means for inhibiting an address translation of addresses in said table means when said inhibiting means is set and for allowing an address translation of addresses in said table means when said inhibiting means is not set, such that addresses not requiring translation are not read out to said address buffer and compare means for translation, a position register for holding a position of an address to be translated, inverting means coupled to said position register for updating said position of said position register for an address to be translated; wherein with an address read out of said table means in which said inhibiting means is set, said position of an address is incremented in said position register wherein said address buffer and compare means comprises second table means having a plurality of storage locations for storing addresses to be translated, each of said storage locations including an active bit position indicating whether an address is active for translation by said translation means, said address buffer and compare means further comprising compare means for comparing addresses in said second table means with an address requested for translation by said detecting means and for entering an address not found in said second table means.