Multiprocessor system featuring global data multiplation

Claim 2

A multiprocessor computing system comprising: a plurality of processors connected in common to a system bus, each processor comprising a processing unit, a local memory and an interface unit connected in common to an internal bus, and said interface unit connecting said internal bus to said system bus, said local memory of each processor including a plurality of addressable storage locations for storing information, a number of said storage locations used to store global data currently in use by said plurality of processors, said processing unit of each processor being connected to have access to said local memory of each of the other processors through said system bus and corresponding interface units for reading or writing information referenced by an address code, said address code comprising a destination code for identifying said local memory into which said information is to be read or written, said each processor further including: first means including said processing unit for generating a destination code in said address code having a binary configuration for identifying said information as global data in response to each write command generated by said processing unit for storing said information in said local memory associated therewith; and second means including said interface unit responsive to said global data binary configuration in said destination code and to said write command from said first means to concurrently perform a write operation of said information identified as a global data into a specified one of said number of storage locations in said local memory associated therewith and broadcast said address code including said global data binary configuration and said write command on said system bus causing all of said other processors to write said information into one of said number of locations of their local memories so that all of said processors are able to have immediate access to said global data.

Claim 3

The multiprocessor system of claim 1 wherein each processor further includes: means responsive to said global data binary configuration on said system bus for acknowledging the execution of said write operation after all said local memories of said other processors accessed in response to said global data binary configuration on said system bus have performed said write operation in response to said write command.

Claim 4

The multiprocessor system of claim 1 wherein said second means of each processor comprises: a decoder coupled to said system bus, said decoder of each other processor being responsive to said global data binary configuration from said system bus to generate an access request signal to said processor associated therewith for directing said address code referencing said local memory on the system bus to said processor.

Claim 5

The multiprocessor system of claim 3 wherein said decoder has a control input connected to receive a signal for inhibiting said decoder from detecting said global data binary configuration on said system bus when said global data binary configuration on said system bus was generated by said each processor.

Claim 6

The multiprocessor of claim 4 wherein said second means further comprising means for converting said global data binary configuration received from said system bus into said destination code for referencing said number of locations of local memory of said each processor used for storing said global data.

Claim 7

A multiprocessor computing system wherein a plurality of active processors are connected in common to a system bus, each processor comprising a processing unit, a local memory, an interface unit and an internal bus connecting in common said processing unit, said local memory and said interface unit, said interface unit of each processor connecting said internal bus to said system bus, said processing unit having access to the local memory of the same processor through said internal bus for performing read and write operations without having to access said system bus, each said processing unit having access to the local memory of each other processor through said system bus for reading out or storing information from or into any one of said local memories referenced by an address code, and in response to read and write commands generated by said processing unit, said address code comprising a destination code identifying which one of said local memories said information is to be written in or read from, each processor further including: first means for generating said address code comprising a destination code having a binary configuration which identifies said information as a global data currently in use by said plurality of said processors for both read and write operations; second means coupled to said first means and responsive to said global data binary configuration in said destination code and said read command generated by said processing unit to select said local memory and perform therein, a read operation at a storage location referenced by said address code without having to access said system bus; third means coupled to said first means and responsive to said global data binary configuration in said destination code and to said write command generated by said processing unit for concurrently selecting the local memory and said interface unit of said each processor to perform a write operation at a storage location referenced by said address code and broadcasting said address code, including said global data binary configuration, and said write command to said system bus; and, fourth means in said each processor connected to said interface unit and responsive to said global data binary configuration on said system bus by any other processor to detect said write command and perform said requested write operation in the local memory of said each processor.

Claim 8

A multiprocessor computing system wherein a plurality of active processors are connected in common to a system bus, each processor comprising a processing unit, a local memory, an interface unit and an internal bus connecting in common said processing unit, said local memory and said interface unit, said interface unit of each processor connecting said internal bus to said system bus, said processing unit having access to the local memory of the same processor through said internal bus for performing read and write operations without having to access said system bus, each said processing unit having access to the local memory of each other processor through said system bus for reading out or storing information from or into any one of said local memories referenced by an address code, and in response to read and write commands generated by said processing unit, said address code comprising a destination code identifying which one of said local memories said information is to be written in or read from, each processor further including: first means for generating said address code comprising a destination code having a binary configuration which identifies said information as a global data currently in use by said plurality of said processors for both read and write operations; second means coupled to said first means and responsive to said global data binary configuration in said destination code and said read command generated by said processing unit to select said local memory and perform therein, a read operation at a storage location referenced by said address code without having to access said system bus; third means coupled to said first means and responsive to said global data binary configuration in said destination code and to said write command generated by said processing unit for concurrently selecting the local memory and said interface unit of said each processor to perform a write operation at a storage location referenced by said address code and broadcasting said address code, including said global data binary configuration, and said write command to said system bus; and, fourth means in said each processor connected to said interface unit and responsive to said global data binary configuration on said system bus by any other processor to detect said write command and perform said requested write operation in the local memory of said each processor.

Claim 9

The multiprocessor system of claim 6 wherein each processor further comprises: fifth means responsive to said global data binary configuration in said destination code and to said write command generated by the same processor, for requesting access to and control over said system bus and for retaining said control over said system bus until a signal is received indicating that said write operation requested by said write command has been performed in the local memories of all other processors.

Claim 10

The multiprocessor of claim 6 wherein said fourth means in each processor comprises means for converting said global data binary configuration received from said system bus into a destination code which references the local memory of the same processor.

Claim 11

The multiprocessor of claim 6 wherein said fourth means comprises: a decoder coupled to said system bus responsive to said global data binary configuration from said system to generate an access request signal to said processor associated therewith for directing said address code to said local memory in said processor, said decoder having a control input connected to receive a signal from said processor for inhibiting said decoder from generating said access request signal when said global data binary configuration on said system bus is broadcasted to said system bus by said third means.