US4598362A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buffer apparatus for controlling access requests among plural memories and plural accessing devices
Assignee: Toshiba Corp
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Filing: 1983-06-21
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Granted: 1986-07-01
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Expires: 2003-06-21
Abstract
Abstract A request buffer apparatus controls a plurality of access requests to devices to be accessed (e.g., memory banks) commonly used by a plurality of accessing devices (e.g., a CPU, channels, and DMA units) in a data processing system. The apparatus has a request buffer means which has a plurality of buffers for storing the access requests. Write/read operations of the requests in and from the request buffer means are randomly performed in accordance with the status of the device to be accessed corresponding to the request stored in the buffer. Requests corresponding to the same device to be accessed are written in the empty buffers of the request buffer means in the order they are generated, and are read out from the request buffer means in the order that they are written. Each device to be accessed has a buffer write address generating means, and the buffer write status of each buffer is indicated so as to obtain the next buffer write address.
Inventors
- 👤 Morishige Kinjo
- 👤 Jyun-ichi Kihara
- 👤 Keizo Aoyagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:26
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1673
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
369 words
A request buffer apparatus for controlling a plurality of access requests which designate a plurality of devices to be accessed, in a data processing system in which said devices to be accessed are shared among a plurality of access devices, comprising: latch register means for latching said access requests from said access devices; request buffer means having k buffers (k>1), coupled to said latch register means, for storing said access requests from said latch register; write control means, coupled to said request buffer means, for monitoring a state of said buffers in said request buffer means to determine addresses of empty buffers, and for writing said access requests, which are latched by said latch register means, in addresses of said empty buffers; buffer read address generating means, coupled to said request buffer means and to said write control means, for sequentially storing written buffer addresses when k access requests which designate a same device to be accessed are written in said buffers in said request buffer means by said write control means, and for generating, as buffer read addresses, said written buffer addresses in an order stored; read control means, coupled to said request buffer means and to said buffer read address generating means, for reading access requests, which are written in said buffers in said request buffer means, based on read addresses supplied by said buffer read address generating means when a device to be accessed is ready to receive access requests; direct data line means, adapted to be coupled between said latch register means and said devices to be accessed, for directly connecting said latch register means with each of said devices to be accessed; and, direct output means, coupled to said latch register means and to said direct data line means, for directly supplying an access request, which is newly latched in said latch register means, through said direct data line means to a device to be accessed, as designated by said newly latched access request, when no access request designating said device designated by said newly latched access request is stored in said request buffer means when said device designated for accessing by said newly latched access request is ready to receive an access request.
Claim 2
Dependent Claim
369 words
A request buffer apparatus for controlling a plurality of access requests which designate a plurality of devices to be accessed, in a data processing system in which said devices to be accessed are shared among a plurality of access devices, comprising: latch register means for latching said access requests from said access devices; request buffer means having k buffers (k>1), coupled to said latch register means, for storing said access requests from said latch register; write control means, coupled to said request buffer means, for monitoring a state of said buffers in said request buffer means to determine addresses of empty buffers, and for writing said access requests, which are latched by said latch register means, in addresses of said empty buffers; buffer read address generating means, coupled to said request buffer means and to said write control means, for sequentially storing written buffer addresses when k access requests which designate a same device to be accessed are written in said buffers in said request buffer means by said write control means, and for generating, as buffer read addresses, said written buffer addresses in an order stored; read control means, coupled to said request buffer means and to said buffer read address generating means, for reading access requests, which are written in said buffers in said request buffer means, based on read addresses supplied by said buffer read address generating means when a device to be accessed is ready to receive access requests; direct data line means, adapted to be coupled between said latch register means and said devices to be accessed, for directly connecting said latch register means with each of said devices to be accessed; and, direct output means, coupled to said latch register means and to said direct data line means, for directly supplying an access request, which is newly latched in said latch register means, through said direct data line means to a device to be accessed, as designated by said newly latched access request, when no access request designating said device designated by said newly latched access request is stored in said request buffer means when said device designated for accessing by said newly latched access request is ready to receive an access request.
Claim 3
Dependent Claim
71 words
An apparatus as in claim 1 wherein said write control means comprises buffer status circuit means, coupled to said request buffer means, for indicating an empty status of said k buffers; and, buffer write address generating means, coupled to said buffer status circuit means, for generating a buffer write address for writing an access request which is received next, in accordance with an output signal from said buffer status circuit means.
Claim 4
Dependent Claim
51 words
An apparatus as in claim 2, wherein said buffer status circuit means comprises a plurality of flip-flops which correspond, respectively, to said k buffers, said plurality of flip-flops being set by a decoded signal of a buffer write address and being reset by a decoded signal of a buffer read address.
Claim 5
Dependent Claim
85 words
An apparatus as in claim 3 wherein said buffer read address generating means comprises counting means for counting a number of access requests to said devices to be accessed which are written in said request buffer means; and, buffer write address saving means, coupled to said buffer write address generating means, for shifting and saving buffer write addresses supplied to said request buffer means from said buffer write address generating means in accordance with a write operation of each request in said request buffer means.
Claim 6
Dependent Claim
61 words
An apparatus as in claim 4, wherein said counting means is incremented in response to a write request signal to said request buffer means for writing an access request to said device to be accessed and is decremented in response to a read request signal to said request buffer means for reading out a request from said device to be accessed.
Claim 7
Dependent Claim
35 words
An apparatus as in claim 4, wherein an output signal from said buffer write address saving means is selected by a selection signal from said counting means so as to obtain a buffer read address.
Claim 8
Dependent Claim
46 words
An apparatus as in claim 2, wherein said buffer write address generating means generates a smallest buffer write address among buffer write addresses that correspond to empty buffers when said buffer status circuit means indicates that a plurality of said buffers are in an empty state.
Claim 9
Dependent Claim
25 words
An apparatus as in claim 1, wherein said buffer read address generating means is provided for each of said plurality of devices to be accessed.
Claim 10
Dependent Claim
85 words
An apparatus as in claim 1, wherein said buffer read address generating means comprises counting means for counting a number of access requests to said devices to be accessed which are written in said request buffer means; and, buffer write address saving means, coupled to said buffer write address generating means, for shifting and saving buffer write addresses supplied to said request buffer means from said buffer write address generating means in accordance with a write operation of each request in said request buffer means.
Claim 11
Dependent Claim
61 words
An apparatus as in claim 9, wherein said counting means is incremented in response to a write request signal to said request buffer means for writing an access request to said device to be accessed, and is decremented in response to a read request signal to said request buffer means for reading out a request from said device to be accessed.
Claim 12
Dependent Claim
35 words
An apparatus as in claim 9, wherein an output signal from said buffer write address saving means is selected by a selection signal from said counting means so as to obtain a buffer read address.
Claim 13
Dependent Claim
233 words
A request buffer apparatus for controlling a plurality of requests to a plurality of memory banks to be accessed which are commonly used by a plurality of accessing devices in a data processing system, comprising: request buffer means having a plurality of buffers for storing access requests to said memory banks; buffer status circuit means, coupled to said request buffer means, for indicating an empty status of said plurality of buffers; buffer write address generating means, coupled to said buffer status circuit means, for generating addresses of said buffers which are empty as buffer write addresses in accordance with contents of said buffer status circuit means; buffer read address generating means, coupled to said request buffer means and said buffer write address generating means, arranged for each of said memory banks, for storing buffer write addresses of said buffers, for storing an access request corresponding to a memory bank, and for generating as a buffer read address to said request buffer means a write address of a buffer storing an access request which is stored first when a buffer read request is received; and, a control circuit, coupled to said buffer read address generating means and said request buffer means, for producing a buffer read request to said buffer read address generating means and a read command to said request buffer means, respectively, in accordance with a ready state of a memory bank.
Claim 14
Dependent Claim
233 words
A request buffer apparatus for controlling a plurality of requests to a plurality of memory banks to be accessed which are commonly used by a plurality of accessing devices in a data processing system, comprising: request buffer means having a plurality of buffers for storing access requests to said memory banks; buffer status circuit means, coupled to said request buffer means, for indicating an empty status of said plurality of buffers; buffer write address generating means, coupled to said buffer status circuit means, for generating addresses of said buffers which are empty as buffer write addresses in accordance with contents of said buffer status circuit means; buffer read address generating means, coupled to said request buffer means and said buffer write address generating means, arranged for each of said memory banks, for storing buffer write addresses of said buffers, for storing an access request corresponding to a memory bank, and for generating as a buffer read address to said request buffer means a write address of a buffer storing an access request which is stored first when a buffer read request is received; and, a control circuit, coupled to said buffer read address generating means and said request buffer means, for producing a buffer read request to said buffer read address generating means and a read command to said request buffer means, respectively, in accordance with a ready state of a memory bank.
Claim 15
Dependent Claim
262 words
A request buffer apparatus adapted to be coupled between a plurality of memory banks and a plurality of access devices, which controls memory access requests sent from said access devices, comprising: latch register means for latching memory access requests that are sent from said access devices; request buffer means, adapted to be coupled between said latch register means and a set of said memory banks, having a plurality of buffers, for storing said memory access requests; request buffer control means, coupled to said request buffer means, for writing, in empty buffers among said buffers, memory access requests which are latched in said latch register means, for searching said buffers for a memory access request which designates a memory bank which is ready to receive a memory access request, and for reading such a memory access request; direct data line means, adapted to be coupled between said latch register means and said memory banks, for directly connecting said latch register means with each of said memory banks; direct output means, coupled to said latch register means and to said direct data line means, for directly supplying a memory access request, which is newly latched in said latch register means, through said direct data line means to a memory bank which is designated by said newly latched memory access request when no memory access request designating said memory bank designated by said newly latched memory access request is stored in said request buffer means when said memory bank designated by said newly latched memory access request is ready to receive a memory access request.
Claim 16
Dependent Claim
262 words
A request buffer apparatus adapted to be coupled between a plurality of memory banks and a plurality of access devices, which controls memory access requests sent from said access devices, comprising: latch register means for latching memory access requests that are sent from said access devices; request buffer means, adapted to be coupled between said latch register means and a set of said memory banks, having a plurality of buffers, for storing said memory access requests; request buffer control means, coupled to said request buffer means, for writing, in empty buffers among said buffers, memory access requests which are latched in said latch register means, for searching said buffers for a memory access request which designates a memory bank which is ready to receive a memory access request, and for reading such a memory access request; direct data line means, adapted to be coupled between said latch register means and said memory banks, for directly connecting said latch register means with each of said memory banks; direct output means, coupled to said latch register means and to said direct data line means, for directly supplying a memory access request, which is newly latched in said latch register means, through said direct data line means to a memory bank which is designated by said newly latched memory access request when no memory access request designating said memory bank designated by said newly latched memory access request is stored in said request buffer means when said memory bank designated by said newly latched memory access request is ready to receive a memory access request.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-30 | 1989-12-30 | 1990-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-30 | 1993-12-30 | 1994-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-30 | 1997-12-30 | 1998-07-01 | $7700.00 | Window Closed / Lapsed |