Interrupt system for peripheral controller

Claim 1

In a network support processor which operates as a peripheral controller for data transfers between a host computer and a line communications processor connecting data communication lines to remote terminals and wherein said network support processor includes first and second processor-controller means each connected to a shared memory means and said first processor-controller means controls an interface circuit connecting said main host computer and said line communications processor to said network support processor, and wherein said interface circuit and said first processor-controller means operate to control data transfers between said host computer and said line communications processor and wherein said shared memory means temporarily stores data-undergoing-transfer while said second processor-controller means operates to edit and format said data-undergoing-transfer, and wherein said interface circuit and said first processor-controller means include an interrupt circuit means, said interrupt circuit means comprising: (a) a first processor means, located in said first processor-controller means, and operating to provide command signals to said interface circuit, said first processor means including: (a1) gating means to generate an interrupt acknowledge signal to an interrupt address register in said interface circuit, said gating means connected to receive an interrupt request signal from a PROM sequencer; (a2) program counter means to provide addresses for instructions in an internal program PROM; (a3) said internal program PROM for storing program instructions for delivery to an instruction-decoder; (a4) said instruction-decoder for executing instructions received from said internal program PROM and for setting bistable means to indicate an interrupt mode signal or normal mode signal; (a5) said bistable means, actuated by said instruction decoder, for generating said normal mode signal or interrupt mode signal to said gating means; (a6) said gating means responsive to said interrupt mode signal for inhibiting the generation of said interrupt acknowledge signal to said interrupt address register; (b) said interface circuit, activated by said first processor-controller means, and providing synchronous communication to said host computer and asynchronous communication to said line communications processor, said interface circuit including: (b1) said PROM sequencer for generating data transfer instructions for data transfer between said host computer or said line communications processor to/from said shared memory means, said sequencer including: (b1a) said interrupt request signal to said instruction-decoder of said first processor means for signalling an interrupt when a data transfer sequence is completed by said PROM sequencer, said interrupt request signal being also connected to said gating means; (b2) a start address register connected to receive address data from said program counter means for initiating an instruction sequence in said PROM sequencer; (b3) said interrupt address register which is hardwired to place the program address of the interrupt instruction routine into said program counter means upon receipt of said interrupt acknowledge signal from said gating means.