Virtual address translation hardware assist circuit and method

Claim 3

A method as set forth in claim 1, wherein the data processor has at least one central processor unit (CPU) that includes a translation buffer, wherein the steps of selectively combining are accomplished by circuit means that is external to the CPU, and wherein the steps of accessing are accomplished by the CPU.

Claim 4

A method as set forth in claim 1 wherein the step of selectively combining the Page field portion of the first register with a content of the STE includes a step of: storing at least a portion of the content of the STE; and wherein the step of selectively combining a portion of the content of the STE with the content of the PTE includes the step of, logically combining the stored portion of the STE with a portion of the content of the PTE; and wherein the step of outputting the combination includes a step of outputting a physical page number portion of the PTE with the logical combination.

Claim 5

A method as set forth in claim 1 wherein the step (b) of forming a first memory address of the ZTE by selectively combining the Zone field portion of the first register with the content of the second register includes a step of adding a physical address of the Zone Table in the second register with the Zone field portion of the faulted virtual address stored within the first register.

Claim 6

A method as set forth in claim 1 wherein the step (c) of forming a second memory address of the STE by selectively combining the Segment field portion of the first register with the content of the ZTE includes a step of concatenating a physical address of the Segment Table read from the ZTE with the Segment field portion of the faulted virtual address stored within the first register.

Claim 7

A method as set forth in claim 1 wherein the step (d) of forming a third memory address of the PTE by selectively combining the Page field portion of the first register with the content of the STE includes a step of concatenating a physical address of the Page Table read from the STE with the Page field portion of the faulted virtual address stored within the first register.

Claim 8

A method as set forth in claim 1 wherein, if any of the steps of simultaneously testing indicate a true condition, the method includes a step of terminating the generation of the entry for the translation buffer.

Claim 9

Circuitry for assisting in the generation of an entry for a translation buffer in a micro-coded data processor that employs virtual memory addressing, comprising: first register means for storing a Faulted Virtual Address and second register means for storing a Zone Table Address (ZTA), a stored Faulted Virtual Address comprising a Zone field portion, a Segment field portion, and a Page field portion, said first and second register means each being loadable in response to the execution of preliminary micro-instructions of a translate virtual address macroinstruction; means, responsive to the execution of a first, subsequent micro-instruction of the translate virtual address macroinstruction, for forming a first memory address of a Zone Table Entry (ZTE) by selectively combining the Zone field portion of the first register with a content of the second register; means, responsive to an execution of a next, second micro-instruction of the translate virtual address macroinstruction, for accessing the ZTE with the first memory address and for forming a second memory address of a Segment Table Entry (STE) by selectively combining the Segment field portion of the first register with a content of the ZTE; means, responsive to an execution of a next, third micro-instruction of the translate virtual address macroinstruction, for accessing the STE with the second memory address and for forming a third memory address of a Page Table Entry (PTE) by selectively combining the Page field portion of the first register with a content of the STE; means, responsive to an execution of a next, fourth micro-instruction of the translate virtual address macroinstruction, for accessing the PTE with the third memory address and for selectively combining a portion of the STE with the content of the PTE and outputting the combination as a generated translation buffer entry; and means, responsive to the execution of the first, subsequent micro-instruction of the translate virtual address macroinstruction, for testing the ZTA for physical address mapping, said testing means being further responsive to the execution of the second micro-instruction of the translate virtual address macroinstruction for testing the ZTE for a Zone fault; to the execution of the third micro-instruction of the translate virtual address macroinstruction for testing the STE for a Segment fault; and to the execution of the fourth micro-instruction of the translate virtual address macroinstruction for testing the PTE for a Page fault.

Claim 10

Circuitry for assisting in the generation of an entry for a translation buffer in a micro-coded data processor that employs virtual memory addressing, comprising: first register means for storing a Faulted Virtual Address and second register means for storing a Zone Table Address (ZTA), a stored Faulted Virtual Address comprising a Zone field portion, a Segment field portion, and a Page field portion, said first and second register means each being loadable in response to the execution of preliminary micro-instructions of a translate virtual address macroinstruction; means, responsive to the execution of a first, subsequent micro-instruction of the translate virtual address macroinstruction, for forming a first memory address of a Zone Table Entry (ZTE) by selectively combining the Zone field portion of the first register with a content of the second register; means, responsive to an execution of a next, second micro-instruction of the translate virtual address macroinstruction, for accessing the ZTE with the first memory address and for forming a second memory address of a Segment Table Entry (STE) by selectively combining the Segment field portion of the first register with a content of the ZTE; means, responsive to an execution of a next, third micro-instruction of the translate virtual address macroinstruction, for accessing the STE with the second memory address and for forming a third memory address of a Page Table Entry (PTE) by selectively combining the Page field portion of the first register with a content of the STE; means, responsive to an execution of a next, fourth micro-instruction of the translate virtual address macroinstruction, for accessing the PTE with the third memory address and for selectively combining a portion of the STE with the content of the PTE and outputting the combination as a generated translation buffer entry; and means, responsive to the execution of the first, subsequent micro-instruction of the translate virtual address macroinstruction, for testing the ZTA for physical address mapping, said testing means being further responsive to the execution of the second micro-instruction of the translate virtual address macroinstruction for testing the ZTE for a Zone fault; to the execution of the third micro-instruction of the translate virtual address macroinstruction for testing the STE for a Segment fault; and to the execution of the fourth micro-instruction of the translate virtual address macroinstruction for testing the PTE for a Page fault.

Claim 11

Circuitry as set forth in claim 8, wherein the data processor has at least one central processor unit (CPU) that includes a translation buffer, and wherein said means for selectively combining are located external to the CPU.

Claim 12

Circuitry as set forth in claim 9 wherein said CPU is coupled to an output of said combining means by a data bus, and wherein said CPU includes a physical address register that is coupled to the data bus for receiving the first, second, and third memory addresses therefrom.

Claim 13

Circuitry as set forth in claim 8 wherein said means for selectively combining a portion of the STE with the content of the PTE includes: register means for storing at least a portion of the content of the STE; and means for logically combining the stored portion with a portion of the content of the PTE; and wherein said means for outputting the combination outputs a physical page number portion of the PTE with an output of said means for logically combining.

Claim 14

Circuitry as set forth in claim 8 wherein said means for forming a first memory address of the ZTE includes means for adding a physical address of the Zone Table in said second register means with the Zone field portion of the faulted virtual address stored within said first register means.

Claim 15

Circuitry as set forth in claim 8 wherein said means for forming a second memory address of the STE includes means for concatenating a physical address of the Segment Table read from the ZTE with the Segment field portion of the faulted virtual address stored within said first register means.

Claim 16

Circuitry as set forth in claim 8 wherein said means for forming a third memory address of the PTE includes means for concatenating a physical address of the Page Table read from the STE with the Page field portion of the faulted virtual address stored within said first register means.

Claim 17

Circuitry as set forth in claim 8 wherein said means for testing includes: means for selectively outputting at least one bit from said second register means and from the content read from one of the ZTE, STE and PTE; and micro-code means for testing a state of the outputted at least one bit.