Parallel protection checking in an address translation look-aside buffer

Claim 2

A virtual memory management system for a processor for providing an output physical address to access a physical location in response to an input virtual address comprising: a single associative memory means for storing multiple virtual addresses, an equal multiple of respectively corresponding physical addresses, and an equal multiple of respectively corresponding sets of status bits; each set of status bits indicating access right of its corresponding physical address to a specific physical location, each set of status bits containing at least one status bit; comparator means coupled to receive said input virtual address and also coupled to receive said multiple virtual addresses for comparing said input virtual address with said multiple virtual addresses to determine if a matching multiple virtual address exists among those addresses compared; fault detection circuit means coupled to said memory means for receiving said sets of status bits corresponding to said physical addresses and determining if a current access request of each of said physical addresses is permitted by its set of status bits, said fault detection circuit means performing its access check simultaneously with said comparing of said input virtual address with said multiple virtual addresses and generating a fault indication signal for each of said physical addresses, which fault indication signal is of the type that prohibits access of said specific physical location if said set of status bits indicates that said current access request is prohibited; and selector means coupled to said memory means, comparator means and fault detection circuit means for selecting a physical address corresponding to said matching multiple virtual address as said output physical address and its corresponding fault indication signal as an output fault indication signal if a match results in said comparator, in order to access said physical location if said output fault indication signal permits said access, such that the fault indication signal and the physical address are provided in a single clock cycle.

Claim 3

The virtual memory management system of claim 1 wherein said memory means is a cache memory.

Claim 4

A virtual memory management system of claim 1 wherein said memory means is a four-way set associative cache memory.

Claim 5

The virtual memory management system of claim 1 wherein said memory is a four-way set associative cache memory implemented in four random access memory arrays.

Claim 6

A virtual memory management system for a processor for providing a portion of an output physical address (output physical address tag) to access a physical location in response to an input virtual address comprising: a single associative memory means for storing multiple virtual addresses, an equal multiple of respectively corresponding physical address tags, and an equal multiple of respectively corresponding sets of status bits; each set of status bits indicating access right of its corresponding physical address to a specific physical location, each set of status bit containing at least one status bit; comparator means coupled to receive said input virtual address and also coupled to receive said multiple virtual addresses for comparing said input virtual address with said multiple virtual addresses to determine if a matching multiple virtual address exists among those addresses compared; fault detection circuit means coupled to said memory means for receiving said sets of status bits corresponding to said physical address tags and determining if a current access request of each of said physical address tags is permitted by its set of status bits, said fault detection circuit means performing its access check simultaneously with said comparing of said input virtual address with said multiple virtual addresses and generating a fault indication signal for each of said physical address tags which fault indication signal is of the type that prohibits access of said specific physical location if said set of status bits indicates that said current access request is prohibited; and selector means coupled to said memory means, comparator means and fault detection circuit means for selecting a physical address tag corresponding to said matching multiple virtual address as said output physical address tag and its corresponding fault indication signal as an output fault indication signal to access said physical location, only if said comparator means find said matching multiple virtual address and said fault detection circuit permits said requested access, such that the fault indication signal and the physical address are provided in a single clock cycle.

Claim 7

A virtual memory management system for a processor for providing a portion of an output physical address (output physical address tag) to access a physical location in response to an input virtual address comprising: a single associative memory means for storing multiple virtual addresses, an equal multiple of respectively corresponding physical address tags, and an equal multiple of respectively corresponding sets of status bits; each set of status bits indicating access right of its corresponding physical address to a specific physical location, each set of status bit containing at least one status bit; comparator means coupled to receive said input virtual address and also coupled to receive said multiple virtual addresses for comparing said input virtual address with said multiple virtual addresses to determine if a matching multiple virtual address exists among those addresses compared; fault detection circuit means coupled to said memory means for receiving said sets of status bits corresponding to said physical address tags and determining if a current access request of each of said physical address tags is permitted by its set of status bits, said fault detection circuit means performing its access check simultaneously with said comparing of said input virtual address with said multiple virtual addresses and generating a fault indication signal for each of said physical address tags which fault indication signal is of the type that prohibits access of said specific physical location if said set of status bits indicates that said current access request is prohibited; and selector means coupled to said memory means, comparator means and fault detection circuit means for selecting a physical address tag corresponding to said matching multiple virtual address as said output physical address tag and its corresponding fault indication signal as an output fault indication signal to access said physical location, only if said comparator means find said matching multiple virtual address and said fault detection circuit permits said requested access, such that the fault indication signal and the physical address are provided in a single clock cycle.

Claim 8

The virtual memory management system of claim 5 wherein said memory means is a cache memory.

Claim 9

The virtual memory management system of claim 5 wherein said memory means is a four-way set associative cache memory for storing four selected virtual addresses and corresponding physical addresses and status bits.

Claim 10

The virtual memory management system of claim 5 wherein said memory is a four-way set associative cache memory implemented in four random access memory arrays.

Claim 11

A virtual memory management system for a processor for providing an output physical address tag to access a physical location in response to an input virtual address comprising: a single associative buffer memory for storing multiple virtual address tags, an equal multiple of respectively corresponding physical address tags, and an equal multiple of respectively corresponding sets of status bits; each set of status bits indicating access right of its corresponding physical address to a specific physical location, each set of status bits containing at least one status bit; a comparator coupled to receive a virtual address tag of said input virtual address and also coupled to receive said multiple virtual address tags for comparing said multiple virtual address tags with said virtual address tag of said input virtual address to determine if a matching multiple virtual address tag exists among those address tags compared; a fault detection circuit coupled to said buffer memory for receiving said sets of status bits corresponding to said physical address tags and determining if a current access request of each of said physical address tags is permitted by its set of status bits, said fault detection circuit performing its access check simultaneously with said comparing of said multiple virtual address tags with said virtual address tag of said input virtual address and generating a fault indication signal for each of said physical address tags, which fault indication signal is of the type that prohibits access of said specific physical location if said set of status bits indicates that said current access request is prohibited; and a multiplexer coupled to said buffer memory, comparator and fault detection circuit for selecting a physical address tag corresponding to said matching multiple virtual address tag as said output physical address tag and its corresponding fault indication signal as an output fault indication signal to access said physical location, only if said comparator finds a matching multiple virtual address tag and said fault detection circuit permits said requested access, such that the fault indication signal and the physical address are provided in a single clock cycle.

Claim 12

A virtual memory management system for a processor for providing an output physical address tag to access a physical location in response to an input virtual address comprising: a single associative buffer memory for storing multiple virtual address tags, an equal multiple of respectively corresponding physical address tags, and an equal multiple of respectively corresponding sets of status bits; each set of status bits indicating access right of its corresponding physical address to a specific physical location, each set of status bits containing at least one status bit; a comparator coupled to receive a virtual address tag of said input virtual address and also coupled to receive said multiple virtual address tags for comparing said multiple virtual address tags with said virtual address tag of said input virtual address to determine if a matching multiple virtual address tag exists among those address tags compared; a fault detection circuit coupled to said buffer memory for receiving said sets of status bits corresponding to said physical address tags and determining if a current access request of each of said physical address tags is permitted by its set of status bits, said fault detection circuit performing its access check simultaneously with said comparing of said multiple virtual address tags with said virtual address tag of said input virtual address and generating a fault indication signal for each of said physical address tags, which fault indication signal is of the type that prohibits access of said specific physical location if said set of status bits indicates that said current access request is prohibited; and a multiplexer coupled to said buffer memory, comparator and fault detection circuit for selecting a physical address tag corresponding to said matching multiple virtual address tag as said output physical address tag and its corresponding fault indication signal as an output fault indication signal to access said physical location, only if said comparator finds a matching multiple virtual address tag and said fault detection circuit permits said requested access, such that the fault indication signal and the physical address are provided in a single clock cycle.

Claim 13

The virtual memory management system of claim 9 wherein said fault detection circuit comprises a plurality of said fault detection circuit means, one of said fault detection circuits for each physical address tag stored.

Claim 14

The virtual memory management system of claim 10 wherein said buffer memory is a cache memory.

Claim 15

The virtual memory management system of claim 10 wherein said buffer memory is a four-way set associative cache memory for storing four selected virtual address tags and corresponding physical address tags and status bits.

Claim 16

The virtual memory management system of claim 10 wherein said buffer memory is a four-way set associative cache memory having four random access memory arrays.

Claim 17

In a virtual memory system for a computer including a single physical memory, means for storing information in said physical memory, means for providing virtual addresses representing locations in said physical memory at which information is stored, and means for translating said virtual addresses to physical addresses for accessing locations in said physical memory, the improvement comprising a buffer memory containing a plurality of stored virtual addresses and corresponding physical addresses utilized by said computer, means for addressing said buffer memory by an input virtual address, means for comparing said input virtual address to said stored virtual addresses, means for selecting a physical address from said buffer memory if said input virtual address matches one of said stored virtual addresses, and means for determining if access to said physical address is permitted at the same time as said input virtual address is compared to said stored virtual addresses, such that the access to the physical address and the physical address are provided in a single clock cycle.

Claim 18

In a virtual memory system for a computer including a single physical memory, means for storing information in said physical memory, means for providing virtual addresses representing locations in said physical memory at which information is stored, and means for translating said virtual addresses to physical addresses for accessing locations in said physical memory, the improvement comprising a buffer memory containing a plurality of stored virtual addresses and corresponding physical addresses utilized by said computer, means for addressing said buffer memory by an input virtual address, means for comparing said input virtual address to said stored virtual addresses, means for selecting a physical address from said buffer memory if said input virtual address matches one of said stored virtual addresses, and means for determining if access to said physical address is permitted at the same time as said input virtual address is compared to said stored virtual addresses, such that the access to the physical address and the physical address are provided in a single clock cycle.

Claim 19

The virtual memory system of claim 14 wherein said buffer memory is a cache memory.

Claim 20

The virtual memory system of claim 15 wherein said indication of said access violation is determined by a mode of operation being performed by said computer.

Claim 21

In a method of operating a virtual memory system for a computer including a single physical memory, means for storing information in said physical memory, means for providing virtual addresses representing locations in said physical memory at which information is stored, and means for translating said virtual addresses to physical addresses for accessing locations in said physical memory at which information is stored, the improvement comprising the steps of: storing a plurality of virtual addresses and corresponding physical addresses in a buffer for use by said computer; addressing said buffer memory by an input virtual address; comparing said input virtual address to said plurality of virtual addresses; selecting from said buffer memory a physical address corresponding to one of said plurality of virtual addresses if said input virtual address matches said one of said plurality of virtual addresses; and determining if access to said physical address is permitted at the same time as said input virtual address is compared to said stored virtual addresses, such that the access to the physical address and the physical address are provided in a single clock cycle.

Claim 22

In a method of operating a virtual memory system for a computer including a single physical memory, means for storing information in said physical memory, means for providing virtual addresses representing locations in said physical memory at which information is stored, and means for translating said virtual addresses to physical addresses for accessing locations in said physical memory at which information is stored, the improvement comprising the steps of: storing a plurality of virtual addresses and corresponding physical addresses in a buffer for use by said computer; addressing said buffer memory by an input virtual address; comparing said input virtual address to said plurality of virtual addresses; selecting from said buffer memory a physical address corresponding to one of said plurality of virtual addresses if said input virtual address matches said one of said plurality of virtual addresses; and determining if access to said physical address is permitted at the same time as said input virtual address is compared to said stored virtual addresses, such that the access to the physical address and the physical address are provided in a single clock cycle.