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US5478769A
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Process for fabricating a stashed capacitor in a semiconductor device
Assignee: SK Hynix Inc
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Filing: 1994-12-28
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Granted: 1995-12-26
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Expires: 2014-12-28
Abstract
Abstract There is a process for fabricating a capacitor of a semiconductor device, distinguished by characteristic steps consisting broadly of laminating an impurity-doped amorphous layer and a pure amorphous layer, alternately and in at least two folds, annealing the multiplicate amorphous layer to polycrystallize it and to diffuse the impurities, utilizing an oxide pattern and a nitride spacer formed at the sidewall of the oxide pattern to form a cylindrical storage electrode consisting of the resulting polysilicon layers, and taking advantage of etch selectivity difference between the doped and undoped polysilicon layers to form grooves in the cylindrical storage electrode. Such storage electrode has a larger surface area than conventional storage electrodes do, in the same space occupied. Therefore, the fabrication process brings about effects that the high integration of semiconductor device can be accomplished and the reliability of device operation can be improved.
Inventors
- 👤 Chan Lim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:30
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716; H10D1/714
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
269 words
A process of the fabrication of capacitor of a semiconductor device, comprising the steps of: forming a MOS transistor on a semiconductor substrate; forming an insulation layer for planarization over the MOS transistor; forming an oxide layer on the insulation layer for planarization; forming a contact hole, to expose a source region of the transistor therethrough; forming a doped first amorphous silicon layer to contact the source region; forming an undoped second amorphous silicon layer, a doped third amorphous silicon layer, an undoped fourth amorphous silicon layer, a doped fifth amorphous silicon layer, and an undoped sixth amorphous silicon layer on the doped first amorphous silicon layer, in sequence; annealing the first through the sixth amorphous silicon layers, to polycrystallize them into a first through a sixth polysilicon layers, respectively; forming an insulation layer pattern on the sixth polysilicon layer such that the insulation layer pattern overlaps with the contact hole; forming a spacer at a sidewall of the insulation layer pattern; etching the sixth through the third polysilicon layers with the spacer and insulation layer pattern serving as a mask; eliminating the insulation layer pattern; simultaneously etching the sixth through the second polysilicon layers in the inside of the spacer and the second and the first polysilicon layers in the outside of the spacer to form a cylindrical storage electrode with the spacer serving as a mask; removing the spacer; etching the doped first, third and fifth polysilicon layers of the storage electrode with a chemical etchant, to form grooves in the sidewall of the storage electrode, whereby the surface area of the storage electrode can be increased.
Claim 2
Dependent Claim
269 words
A process of the fabrication of capacitor of a semiconductor device, comprising the steps of: forming a MOS transistor on a semiconductor substrate; forming an insulation layer for planarization over the MOS transistor; forming an oxide layer on the insulation layer for planarization; forming a contact hole, to expose a source region of the transistor therethrough; forming a doped first amorphous silicon layer to contact the source region; forming an undoped second amorphous silicon layer, a doped third amorphous silicon layer, an undoped fourth amorphous silicon layer, a doped fifth amorphous silicon layer, and an undoped sixth amorphous silicon layer on the doped first amorphous silicon layer, in sequence; annealing the first through the sixth amorphous silicon layers, to polycrystallize them into a first through a sixth polysilicon layers, respectively; forming an insulation layer pattern on the sixth polysilicon layer such that the insulation layer pattern overlaps with the contact hole; forming a spacer at a sidewall of the insulation layer pattern; etching the sixth through the third polysilicon layers with the spacer and insulation layer pattern serving as a mask; eliminating the insulation layer pattern; simultaneously etching the sixth through the second polysilicon layers in the inside of the spacer and the second and the first polysilicon layers in the outside of the spacer to form a cylindrical storage electrode with the spacer serving as a mask; removing the spacer; etching the doped first, third and fifth polysilicon layers of the storage electrode with a chemical etchant, to form grooves in the sidewall of the storage electrode, whereby the surface area of the storage electrode can be increased.
Claim 3
Dependent Claim
32 words
A process in accordance with claim 1, wherein said spacer is formed from a material which is different in etch selectivity from both said insulation layer pattern and said sixth polysilicon layer.
Claim 4
Dependent Claim
40 words
A process in accordance with claim 1, wherein said chemical etchant is a mixed solution of nitric acid, acetic acid, hydrofluoric acid and deionized water with the volume ratio of nitric acid: acetic acid: hydrofluoric acid: deionized water being 30:3:0.5:15.5.
Claim 5
Dependent Claim
52 words
A process in accordance with claim 1, wherein said oxide layer formed on the insulation layer for planarization is removed by the same chemical etchant that is used for etching the doped first, third and fifth polysilicon layers of the storage electrode to form grooves in the sidewall of the storage electrode.
Claim 6
Dependent Claim
256 words
A process of the fabrication of capacitor of a semiconductor device, comprising the steps of: forming a MOS transistor on a semiconductor substrate; forming an insulation layer for planarization over the MOS transistor; forming an oxide layer on the insulation layer for planarization; forming a contact hole, to expose a source region of the transistor therethrough; forming a doped first amorphous silicon layer to contact the source region; forming an undoped second amorphous silicon layer, a doped third amorphous silicon layer and an undoped fourth amorphous silicon layer on the doped first amorphous silicon layer, in sequence; annealing the first through the fourth amorphous silicon layers, to polycrystallize them into a first through a fourth polysilicon layers, respectively; forming an insulation layer pattern on the fourth polysilicon layer such that the insulation layer pattern overlaps with the contact hole; forming a spacer at a sidewall of the insulation layer pattern; etching the fourth and the third polysilicon layers with the spacer and insulation layer pattern serving as a mask; eliminating the insulation layer pattern; simultaneously etching the fourth through the second polysilicon layers in the inside of the spacer and the second and the first polysilicon layers in the outside of the spacer to form a cylindrical storage electrode with the spacer serving as a mask; removing the spacer; etching the doped first and third polysilicon layers of the storage electrode with a chemical etchant, to form grooves in the sidewall of the storage electrode, whereby the surface area of the storage electrode can be increased.
Claim 7
Dependent Claim
256 words
A process of the fabrication of capacitor of a semiconductor device, comprising the steps of: forming a MOS transistor on a semiconductor substrate; forming an insulation layer for planarization over the MOS transistor; forming an oxide layer on the insulation layer for planarization; forming a contact hole, to expose a source region of the transistor therethrough; forming a doped first amorphous silicon layer to contact the source region; forming an undoped second amorphous silicon layer, a doped third amorphous silicon layer and an undoped fourth amorphous silicon layer on the doped first amorphous silicon layer, in sequence; annealing the first through the fourth amorphous silicon layers, to polycrystallize them into a first through a fourth polysilicon layers, respectively; forming an insulation layer pattern on the fourth polysilicon layer such that the insulation layer pattern overlaps with the contact hole; forming a spacer at a sidewall of the insulation layer pattern; etching the fourth and the third polysilicon layers with the spacer and insulation layer pattern serving as a mask; eliminating the insulation layer pattern; simultaneously etching the fourth through the second polysilicon layers in the inside of the spacer and the second and the first polysilicon layers in the outside of the spacer to form a cylindrical storage electrode with the spacer serving as a mask; removing the spacer; etching the doped first and third polysilicon layers of the storage electrode with a chemical etchant, to form grooves in the sidewall of the storage electrode, whereby the surface area of the storage electrode can be increased.
Claim 8
Dependent Claim
32 words
A process in accordance with claim 5, wherein said spacer is formed from a material which is different in etch selectivity from both said insulation layer pattern and said fourth polysilicon layer.
Claim 9
Dependent Claim
40 words
A process in accordance with claim 5, wherein said chemical etchant is a mixed solution of nitric acid, acetic acid, hydrofluoric acid and deionized water with the volume ratio of nitric acid: acetic acid: hydrofluoric acid: deionized water being 30:3:0.5:15.5.
Claim 10
Dependent Claim
51 words
A process in accordance with claim 7, wherein said oxide layer formed on the insulation layer for planarization is removed by the same chemical etchant that is used for etching the doped first and third polysilicon layers of the storage electrode to form grooves in the sidewall of the storage electrode.
Claim 11
Dependent Claim
27 words
A process in accordance with claim 8, wherein said first through said fourth amorphous layers are annealed at a temperature of about 550° to about 700° C.
References Cited (Backward Citations)
US5053351A
Cited
US5281549A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-12-25 | 1999-06-26 | 1999-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-25 | 2003-06-26 | 2003-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-25 | 2007-06-26 | 2007-12-26 | $7700.00 | Window Closed / Lapsed |