Patent US5477549A successfully refreshed from Google Patents.
US5477549A
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US
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Cell switch and cell switch network using dummy cells for simplified cell switch test in communication network
Assignee: Toshiba Corp
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Filing: 1995-04-11
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Granted: 1995-12-19
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Expires: 2015-04-11
Abstract
Abstract A cell switch and a cell switch network with a simplified cell switch testing such that the testing processes can be carried out quickly and easily. The cell switch includes a dummy cell generation circuit for generating dummy cells in correspondence to the output transmission paths; and an output control circuit for selectively outputting the dummy cells to the output transmission paths when a test of the cell switch is indicated by an externally provided control signal. In a cell switch network in which the cell switches are interconnected in a form of a multi-step configuration, the cell switches belonging to each step in the multi-step configuration of the cell switch network is tested sequentially, by supplying the control signal to each of the cell switches belonging to each step in the multi-step configuration of the cell switch network sequentially, in a reverse order of steps in the multi-step configuration of the cell switch network.
Inventors
- 👤 Eiji Kamagata
- 👤 Yasuro Shobatake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:40
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/108; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L43/00; H04L43/50; H04L49/15; H04L49/1553; H04L49/25; H04L49/253; H04L49/255; H04L49/256; H04L2012/5628
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
237 words
A cell switch network comprising: a plurality of inter-connected cell switches for switching cells entering from a plurality of input transmission paths to a plurality of output transmission paths according to a routing information indicated in a header of each cell, each cell switch including: buffer memory means, connected with the input transmission paths and the output transmission paths, for storing the cells entered from the input transmission paths; buffer memory control means for controlling writing and reading operations with respect to the buffer memory means according to the routing information indicated in a header of each cell; dummy cell generation means for generating dummy cells in correspondence to the output transmission paths, said dummy cells outputted to the output transmission paths and monitored during a test for testing connections of the cell switch; and output control means for selectively outputting the dummy cells generated by the dummy cell generation means to the output transmission paths when the test for testing connections of the cell switch is indicated by an externally provided control signal supplied to the output control means, and selectively outputting the cells outputted from the buffer memory means to the output transmission paths otherwise; wherein a part of said plurality of inter-connected cell switches is subjected to the test for testing connections while a remaining part of said plurality of inter-connected cell switches remain in an operation for switching the cells in the network.
Claim 2
Dependent Claim
237 words
A cell switch network comprising: a plurality of inter-connected cell switches for switching cells entering from a plurality of input transmission paths to a plurality of output transmission paths according to a routing information indicated in a header of each cell, each cell switch including: buffer memory means, connected with the input transmission paths and the output transmission paths, for storing the cells entered from the input transmission paths; buffer memory control means for controlling writing and reading operations with respect to the buffer memory means according to the routing information indicated in a header of each cell; dummy cell generation means for generating dummy cells in correspondence to the output transmission paths, said dummy cells outputted to the output transmission paths and monitored during a test for testing connections of the cell switch; and output control means for selectively outputting the dummy cells generated by the dummy cell generation means to the output transmission paths when the test for testing connections of the cell switch is indicated by an externally provided control signal supplied to the output control means, and selectively outputting the cells outputted from the buffer memory means to the output transmission paths otherwise; wherein a part of said plurality of inter-connected cell switches is subjected to the test for testing connections while a remaining part of said plurality of inter-connected cell switches remain in an operation for switching the cells in the network.
Claim 3
Dependent Claim
58 words
The cell switch network of claim 1, wherein the output transmission paths include a plurality of output channels and each of the dummy cells has a header indicating the routing information specifying one of the output channels of the output transmission paths to which said each of the dummy cells is selectively outputted by the output control means.
Claim 4
Dependent Claim
77 words
The cell switch network of claim 1, further comprising: cell clock input means for inputting externally provided cell clock signals indicating timings for writing and reading of the cells in the cell switch; and cell clock output means for outputting the cell clock signals to other cell switches connected to the output transmission paths of the cell switch in order to check cell input and output operation timings between the cell switch and the other cell switches.
Claim 5
Dependent Claim
71 words
The cell switch network of claim 1, further comprising: system clock input means for inputting externally provided system clock signals indicating timings for switching operations in the cell switch; and system clock output means for outputting the system clock signals to other devices connected to the output transmission paths of the cell switch in order to adjust cell input and output phase relationships between the cell switch and the other devices.
Claim 6
Dependent Claim
20 words
The cell switch network of claim 1, wherein the cell switches are inter-connected in a form of a multi-step configuration.
Claim 7
Dependent Claim
76 words
The cell switch network of claim 5, wherein the output transmission paths includes a plurality of output channels and each of the cells and the dummy cells has a header indicating the routing information specifying one of the output channels of the output transmission paths to which said each of the cells and the dummy cells is to be outputted at the cell switch of each step in the multi-step configuration of the cell switch network.
Claim 8
Dependent Claim
189 words
A cell switch for switching cells entering from a plurality of input transmission paths to a plurality of output transmission paths according to a routing information indicated in a header of each cell, the cell switch comprising: buffer memory means, connected with the input transmission paths and the output transmission paths, for storing the cells entered from the input transmission paths; buffer memory control means for controlling writing and reading operations with respect to the buffer memory means according to the routing information indicated in a header of each cell; dummy cell generation means for generating dummy cells in correspondence to the output transmission paths, said dummy cells outputted to the output transmission paths and monitored during a test for testing connections of the cell switch; and output control means for selectively outputting the dummy cells generated by the dummy cell generation means to the output transmission paths when the test for testing connections of the cell switch is indicated by an externally provided control signal supplied to the output control means, and selectively outputting the cells outputted from the buffer memory means to the output transmission paths otherwise.
Claim 9
Dependent Claim
189 words
A cell switch for switching cells entering from a plurality of input transmission paths to a plurality of output transmission paths according to a routing information indicated in a header of each cell, the cell switch comprising: buffer memory means, connected with the input transmission paths and the output transmission paths, for storing the cells entered from the input transmission paths; buffer memory control means for controlling writing and reading operations with respect to the buffer memory means according to the routing information indicated in a header of each cell; dummy cell generation means for generating dummy cells in correspondence to the output transmission paths, said dummy cells outputted to the output transmission paths and monitored during a test for testing connections of the cell switch; and output control means for selectively outputting the dummy cells generated by the dummy cell generation means to the output transmission paths when the test for testing connections of the cell switch is indicated by an externally provided control signal supplied to the output control means, and selectively outputting the cells outputted from the buffer memory means to the output transmission paths otherwise.
Claim 10
Dependent Claim
57 words
The cell switch of claim 7, wherein the output transmission paths includes a plurality of output channels and each of the dummy cells has a header indicating the routing information specifying one of the output channels of the output transmission paths to which said each of the dummy cells is selectively outputted by the output control means.
Claim 11
Dependent Claim
76 words
The cell switch of claim 7, further comprising: cell clock input means for inputting externally provided cell clock signals indicating timings for writing and reading of the cells in the cell switch; and cell clock output means for outputting the cell clock signals to other cell switches connected to the output transmission paths of the cell switch in order to check cell input and output operation timings between the cell switch and the other cell switches.
Claim 12
Dependent Claim
70 words
The cell switch of claim 7, further comprising: system clock input means for inputting externally provided system clock signals indicating timings for switching operations in the cell switch; and system clock output means for outputting the system clock signals to other devices connected to the output transmission paths of the cell switch in order to adjust cell input and output phase relationships between the cell switch and the other devices.
Claim 13
Dependent Claim
197 words
A cell switch network comprising: a plurality of inter-connected cell switches for switching cells entering from a plurality of input transmission paths to a plurality of output transmission paths according to a routing information indicated in a header of each cell, each cell switch including: buffer memory means, connected with the input transmission paths and the output transmission paths, for storing the cells entered from the input transmission paths; buffer memory control means for controlling writing and reading operations with respect to the buffer memory means according to the routing information indicated in a header of each cell; dummy cell generation means for generating dummy cells in correspondence to the output transmission paths, said dummy cells outputted to the output transmission paths and monitored during a test for testing connections of the cell switch; and output control means for selectively outputting the dummy cells generated by the dummy cell generation means to the output transmission paths when the test for testing connections of the cell switch is indicated by an externally provided control signal supplied to the output control means, and selectively outputting the cells outputted from the buffer memory means to the output transmission paths otherwise.
Claim 14
Dependent Claim
197 words
A cell switch network comprising: a plurality of inter-connected cell switches for switching cells entering from a plurality of input transmission paths to a plurality of output transmission paths according to a routing information indicated in a header of each cell, each cell switch including: buffer memory means, connected with the input transmission paths and the output transmission paths, for storing the cells entered from the input transmission paths; buffer memory control means for controlling writing and reading operations with respect to the buffer memory means according to the routing information indicated in a header of each cell; dummy cell generation means for generating dummy cells in correspondence to the output transmission paths, said dummy cells outputted to the output transmission paths and monitored during a test for testing connections of the cell switch; and output control means for selectively outputting the dummy cells generated by the dummy cell generation means to the output transmission paths when the test for testing connections of the cell switch is indicated by an externally provided control signal supplied to the output control means, and selectively outputting the cells outputted from the buffer memory means to the output transmission paths otherwise.
Claim 15
Dependent Claim
58 words
The cell switch network of claim 11, wherein the output transmission paths includes a plurality of output channels and each of the dummy cells has a header indicating the routing information specifying one of the output channels of the output transmission paths to which said each of the dummy cells is selectively outputted by the output control means.
Claim 16
Dependent Claim
77 words
The cell switch network of claim 11, further comprising: cell clock input means for inputting externally provided cell clock signals indicating timings for writing and reading of the cells in the cell switch; and cell clock output means for outputting the cell clock signals to other cell switches connected to the output transmission paths of the cell switch in order to check cell input and output operation timings between the cell switch and the other cell switches.
Claim 17
Dependent Claim
71 words
The cell switch network of claim 11, further comprising: system clock input means for inputting externally provided system clock signals indicating timings for switching operations in the cell switch; and system clock output means for outputting the system clock signals to other devices connected to the output transmission paths of the cell switch in order to adjust cell input and output phase relationships between the cell switch and the other devices.
Claim 18
Dependent Claim
20 words
The cell switch network of claim 11, wherein the cell switches are interconnected in a form of a multi-step configuration.
Claim 19
Dependent Claim
76 words
The cell switch network of claim 15, wherein the output transmission paths includes a plurality of output channels and each of the cells and the dummy cells has a header indicating the routing information specifying one of the output channels of the output transmission paths to which said each of the cells and the dummy cells is to be outputted at the cell switch of each step in the multi-step configuration of the cell switch network.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |