Patent US5477499A successfully refreshed from Google Patents.
US5477499A
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US
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Memory architecture for a three volt flash EEPROM
Assignee: Cypress Semiconductor Corp
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Filing: 1993-10-13
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Granted: 1995-12-19
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Expires: 2013-10-13
Abstract
Abstract A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage VCC and high speed performance. This high speed performance is achieved by utilizing overerasure, a condition that was previously viewed as making a flash EEPROM cell inoperative, Specifically, the integrated circuit of this invention includes a flash EEPROM array wherein each flash EEPROM cell is overerased, and circuit means which erases, reads, and programs the overerased flash EEPROM cells. In each operation, the circuit means isolates all of the flash EEPROM cells in the array except a selected flash EEPROM cell so that leakage currents do not affect the flash EEPROM cell selected for the operation. The ability to perform the read operation on an overerased flash EEPROM cell is the mechanism that maintains the speed performance of the flash EEPROM array with the low power supply voltage.
Inventors
- 👤 Michael A. Van Buskirk
- 👤 Michael Briner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:41
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; G11C16/10; G11C16/14; G11C16/16; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
117 words
A non-volatile memory structure comprising: a plurality of flash electrically erasable read-only memory (EEPROM) cells; a plurality of bit lines; and a plurality of word lines wherein each flash EEPROM cell is connected to one of said plurality of word lines and to one of said plurality of bit lines; an overerasure circuit operatively connected to said plurality of word lines and to said plurality of bit lines wherein upon erasure of a flash EEPROM cell, said overerasure circuit applies voltages to the word line and to the bit line connected to said flash EEPROM cell such that said flash EEPROM cell has a negative delta threshold thereby placing said flash EEPROM cell in an overerased condition.
Claim 2
Dependent Claim
117 words
A non-volatile memory structure comprising: a plurality of flash electrically erasable read-only memory (EEPROM) cells; a plurality of bit lines; and a plurality of word lines wherein each flash EEPROM cell is connected to one of said plurality of word lines and to one of said plurality of bit lines; an overerasure circuit operatively connected to said plurality of word lines and to said plurality of bit lines wherein upon erasure of a flash EEPROM cell, said overerasure circuit applies voltages to the word line and to the bit line connected to said flash EEPROM cell such that said flash EEPROM cell has a negative delta threshold thereby placing said flash EEPROM cell in an overerased condition.
Claim 3
Dependent Claim
35 words
The non-volatile memory structure of claim 1 wherein said overerasure circuit floats all of said bit lines in said plurality of bit lines except the bit line connected to said flash EEPROM cell being erased.
Claim 4
Dependent Claim
33 words
The non-volatile memory structure of claim 1 wherein said flash EEPROM cell being erased includes a drain connected to said bit line, a source, and a control gate connected to said word line.
Claim 5
Dependent Claim
52 words
The non-volatile memory structure of claim 3 wherein said overerasure circuit applies a first potential to said source and a second potential to said drain wherein said first potential is greater than said second potential so that said source functions electrically as the drain and said drain functions electrically as the source.
Claim 6
Dependent Claim
15 words
The non-volatile memory structure of claim 3 wherein said first potential is about three volts.
Claim 7
Dependent Claim
32 words
The non-volatile memory structure of claim 3 wherein said overerasure circuit applies a voltage -V ERASE R to said word line wherein said voltage -V ERASE R overerases said flash EEPROM cell.
Claim 8
Dependent Claim
24 words
The non-volatile memory structure of claim 1 wherein said overerasure circuit includes a word line control circuit connected to said plurality of word lines.
Claim 9
Dependent Claim
78 words
The non-volatile memory structure of claim 7 wherein said word line control circuit further comprises a switch circuit connected to voltages V PROGRAM R and - PROGRAM R-INHIBIT and to said plurality of words lines wherein to program an overerased flash EEPROM cell, said switch circuit switches voltage V PROGRAM R onto the word line connected to said overerased flash EEPROM cell, and voltage -V PROGRAM R-INHIBIT onto all other word lines in said plurality of word lines.
Claim 10
Dependent Claim
17 words
The non-volatile memory structure of claim 8 wherein said voltage V PROGRAM R-INHIBIT is about 7 volts.
Claim 11
Dependent Claim
17 words
The non-volatile memory structure of claim 8 wherein said voltage V PROGRAM R-INHIBIT is about -2 volts.
Claim 12
Dependent Claim
78 words
The non-volatile memory structure of claim 7 wherein said word line control circuit further comprises a switch circuit connected to voltages V READ R and V READ R-INHIBIT and to said plurality of words lines wherein to read an overerased flash EEPROM cell, said switch circuit switches voltage V READ R onto the word line connected to said overerased flash EEPROM cell, and voltage V READ R-INHIBIT onto all other word lines in said plurality of word lines.
Claim 13
Dependent Claim
21 words
The non-volatile memory structure of claim 11 wherein said voltage V READ R is about power supply voltage V CC .
Claim 14
Dependent Claim
18 words
The non-volatile memory structure of claim 12 wherein said power supply voltage V CC is about three volts.
Claim 15
Dependent Claim
17 words
The non-volatile memory structure of claim 11 wherein said voltage V READ R-INHIBIT is about 0 volts.
Claim 16
Dependent Claim
24 words
The non-volatile memory structure of claim 1 wherein said overerasure circuit includes a bit line control circuit connected to said plurality of bit lines.
Claim 17
Dependent Claim
78 words
The non-volatile memory structure of claim 15 wherein said bit line control circuit further comprises a switch circuit connected to voltages V PROGRAM C and V PROGRAM C-INHIBIT and to said plurality of bit lines wherein to program an overerased flash EEPROM cell, said switch circuit switches voltage V PROGRAM C onto the bit line connected to said overerased flash EEPROM cell, and voltage V PROGRAM C-INHIBIT onto all other bit lines in said plurality of bit lines.
Claim 18
Dependent Claim
23 words
The non-volatile memory structure of claim 16 wherein said voltage V PROGRAM C is about twice a power supply voltage V CC .
Claim 19
Dependent Claim
18 words
The non-volatile memory structure of claim 17 wherein said power supply voltage V CC is about three volts.
Claim 20
Dependent Claim
17 words
The non-volatile memory structure of claim 16 wherein said voltage V PROGRAM C-INHIBIT is about 0 volts.
Claim 21
Dependent Claim
58 words
The non-volatile memory structure of claim 16 wherein said switch circuit includes a position that floats selected bit lines wherein to program said overerased flash EEPROM cell, said switch circuit switches voltage V PROGRAM C onto the bit line connected to said overerased flash EEPROM cell, and floats all other bit lines in said plurality of bit lines.
Claim 22
Dependent Claim
74 words
The non-volatile memory structure of claim 15 wherein said bit line control circuit further comprises a switch circuit connected to voltages V READ C and V READ C-INHIBIT and to said plurality of bit lines wherein to read an overerased flash EEPROM cell, said switch circuit switches voltage V READ C onto the bit line connected to said overerased flash EEPROM cell, and floats all other bit lines in said plurality of bit lines.
Claim 23
Dependent Claim
23 words
The non-volatile memory structure of claim 21 wherein said voltage V READ C is about one-half of power supply voltage V CC .
Claim 24
Dependent Claim
18 words
The non-volatile memory structure of claim 22 wherein said power supply voltage V CC is about three volts.
Claim 25
Dependent Claim
43 words
The non-volatile memory structure of claim 1 where each flash EEPROM cell includes a drain connected to one bit line in said plurality of bit lines; a control gate connected to one word line in said plurality of word lines; and a source.
Claim 26
Dependent Claim
27 words
The non-volatile memory structure of claim 24 wherein said overerasure circuit further comprises a common source control circuit connected to the sources of said flash EEPROM cells.
Claim 27
Dependent Claim
46 words
The non-volatile memory structure of claim 25 wherein said common source control circuit further comprises a switch circuit connected to power supply voltage V CC , to ground, and to said sources wherein to program an overerased flash EEPROM cell, said switch circuit grounds said sources.
Claim 28
Dependent Claim
53 words
The non-volatile memory structure of claim 25 wherein said common source control circuit further comprises a switch circuit connected to power supply voltage V CC , to ground, and to said sources wherein to read an overerased flash EEPROM cell, said switch circuit switches said power supply voltage V CC onto said sources.
Claim 29
Dependent Claim
18 words
The non-volatile memory structure of claim 27 wherein said power supply voltage V CC is about three volts.
Claim 30
Dependent Claim
64 words
A structure comprising: a power supply having a voltage of about three volts; an array, operatively coupled to said power supply, including a plurality of flash electrically erasable read-only memory (EEPROM) cells; a read circuit operatively coupled to said array and to said power supply wherein said read circuit reads a flash EEPROM cell in said array in a time of about 100 nanoseconds.
Claim 31
Dependent Claim
64 words
A structure comprising: a power supply having a voltage of about three volts; an array, operatively coupled to said power supply, including a plurality of flash electrically erasable read-only memory (EEPROM) cells; a read circuit operatively coupled to said array and to said power supply wherein said read circuit reads a flash EEPROM cell in said array in a time of about 100 nanoseconds.
Claim 32
Dependent Claim
45 words
The structure of claim 29 wherein said array further comprises: a plurality of bit lines; and a plurality of word lines wherein each flash EEPROM cell is connected to one of said plurality of word lines and to one of said plurality of bit lines.
Claim 33
Dependent Claim
22 words
The structure of claim 30 wherein said read circuit includes a word line control circuit connected to said plurality of word lines.
Claim 34
Dependent Claim
73 words
The structure of claim 31 wherein said word line control circuit further comprises a switch circuit connected to voltages V READ R and V READ R-INHIBIT and to said plurality of words lines wherein to read a flash EEPROM cell, said switch circuit switches voltage V READ onto the word line connected to said flash EEPROM cell, and voltage V READ INHIBIT onto all other word lines in said plurality of word lines.
Claim 35
Dependent Claim
19 words
The structure of claim 32 wherein said voltage V READ R is about the voltage of said power supply.
Claim 36
Dependent Claim
15 words
The structure of claim 32 wherein said voltage V READ R-INHIBIT is about 0 volts.
Claim 37
Dependent Claim
22 words
The structure of claim 30 wherein said read circuit includes a bit line control circuit connected to said plurality of bit lines.
Claim 38
Dependent Claim
66 words
The structure of claim 35 wherein said bit line control circuit further comprises a switch circuit connected to voltage V READ C and to said plurality of bit lines wherein to read a flash EEPROM cell, said switch circuit switches voltage V READ C onto the bit line connected to said flash EEPROM cell, and floats all other bit lines in said plurality of bit lines.
Claim 39
Dependent Claim
21 words
The structure of claim 36 wherein said voltage V READ C is about one-half of said voltage of said power supply.
Claim 40
Dependent Claim
41 words
The structure of claim 30 where each flash EEPROM cell includes a drain connected to one bit line in said plurality of bit lines; a control gate connected to one word line in said plurality of word lines; and a source.
Claim 41
Dependent Claim
25 words
The structure of claim 38 wherein said reading circuit further comprises a common source control circuit connected to the sources of said flash EEPROM cells.
Claim 42
Dependent Claim
45 words
The structure of claim 39 wherein said common source control circuit further comprises a switch circuit connected to said power supply and to said sources wherein to read an flash EEPROM cell, said switch circuit connects said voltage of said power supply to said sources.
Claim 43
Independent Claim
86 words
A method for operating a flash EEPROM cell having a power supply voltage of about 3 volts to achieve high speed performance comprising the steps of: erasing said flash EEPROM cell to an overerased state; and reading said flash EEPROM cell by raising a source of said flash EEPROM cell to a potential greater than the potential on a bit line connected to a drain of said flash EEPROM cell whereby said source functions electrically as a drain and said drain functions electrically as a source.
Claim 44
Independent Claim
86 words
A method for operating a flash EEPROM cell having a power supply voltage of about 3 volts to achieve high speed performance comprising the steps of: erasing said flash EEPROM cell to an overerased state; and reading said flash EEPROM cell by raising a source of said flash EEPROM cell to a potential greater than the potential on a bit line connected to a drain of said flash EEPROM cell whereby said source functions electrically as a drain and said drain functions electrically as a source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |