US5477466A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and structure for improving patterning design for processing
Assignee: LSI Corp
•
Filing: 1994-12-22
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Granted: 1995-12-19
•
Expires: 2014-12-22
Abstract
Abstract A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.
Inventors
- 👤 Prabhakar P. Tripathi
- 👤 Bruce Whitefield
- 👤 Chi-Hung Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:41
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398; H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/071; H10W20/081; H10W20/089; H10W20/092; H10W20/40
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
173 words
A method of fabricating an integrated circuit, comprising the steps of: (a) generating a circuit layout of said integrated circuit, comprising the substeps of: (a1) determining a surface area of metallization used in said circuit layout; (a2) comparing said surface area with a first predetermined value; (a3) determining a distance between a first working line and a second working line to determine if said first or said second working line is a lonely line; (a4) comparing said distance to a second predetermined value; and if said distance is greater than said second predetermined value, (a5) placing a dummy line at a predetermined distance from said lonely line; (b) forming active regions on an integrated circuit chip; (c) forming a metallization layer on the chip; (d) forming a photoresist layer on the metallization layer; (e) imaging the photoresist layer in accordance with said circuit layout; (f) developing the photoresist layer; (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (h) removing the photoresist layer.
Claim 2
Independent Claim
173 words
A method of fabricating an integrated circuit, comprising the steps of: (a) generating a circuit layout of said integrated circuit, comprising the substeps of: (a1) determining a surface area of metallization used in said circuit layout; (a2) comparing said surface area with a first predetermined value; (a3) determining a distance between a first working line and a second working line to determine if said first or said second working line is a lonely line; (a4) comparing said distance to a second predetermined value; and if said distance is greater than said second predetermined value, (a5) placing a dummy line at a predetermined distance from said lonely line; (b) forming active regions on an integrated circuit chip; (c) forming a metallization layer on the chip; (d) forming a photoresist layer on the metallization layer; (e) imaging the photoresist layer in accordance with said circuit layout; (f) developing the photoresist layer; (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (h) removing the photoresist layer.
Claim 3
Dependent Claim
31 words
A method as in claim 1, in which step (a) further comprises the substep of: (a6) repeating steps (a1) through (a5) until said area is at least said first predetermined value.
Claim 4
Dependent Claim
30 words
A method as in claim 2, in which step (a) further comprises the substep of: (a7) distinguishing said dummy line from said working line; wherein step (a7) follows step (a3).
Claim 5
Independent Claim
207 words
A method of fabricating an integrated circuit, comprising the steps of: (a) generating a circuit layout using a computer, comprising the substeps of: (a1) determining a surface area of said metallization; (a2) comparing said area with a first predetermined value; if said area is less than said first predetermined value, said computer proceeding with the following series of substeps; (a3) initializing a mesh pattern of local wires with physical wires; (a4) removing an overlap between said local and said physical wires; (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires; (a6) removing segments of said local wires of a length less than a second predetermined value; (a7) creating a boundary of a second predetermined distance surrounding said physical wires; and (a8) removing segments of said local wires which are outside said boundary; (b) forming active regions on an integrated circuit chip; (c) forming a metallization layer on the chip; (d) forming a photoresist layer on the metallization layer; (e) imaging the photoresist layer in accordance with said circuit layout; (f) developing the photoresist layer; (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (h) removing the photoresist layer.
Claim 6
Independent Claim
207 words
A method of fabricating an integrated circuit, comprising the steps of: (a) generating a circuit layout using a computer, comprising the substeps of: (a1) determining a surface area of said metallization; (a2) comparing said area with a first predetermined value; if said area is less than said first predetermined value, said computer proceeding with the following series of substeps; (a3) initializing a mesh pattern of local wires with physical wires; (a4) removing an overlap between said local and said physical wires; (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires; (a6) removing segments of said local wires of a length less than a second predetermined value; (a7) creating a boundary of a second predetermined distance surrounding said physical wires; and (a8) removing segments of said local wires which are outside said boundary; (b) forming active regions on an integrated circuit chip; (c) forming a metallization layer on the chip; (d) forming a photoresist layer on the metallization layer; (e) imaging the photoresist layer in accordance with said circuit layout; (f) developing the photoresist layer; (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (h) removing the photoresist layer.
Claim 7
Dependent Claim
49 words
A method as in claim 4, in which step (a) further comprises the substeps of: (a9) changing the characterization of said local wires causing said local wires to appear as physical wires; and (a10) repeating steps (a1) through (a8) until said area is greater than said first predetermined value.
Claim 8
Dependent Claim
31 words
A method as in claim 5, in which step (a) further comprises the substep of: (a11) distinguishing said local wires from said physical wires; wherein step (a11) follows said step (a8).
Claim 9
Independent Claim
213 words
A method of fabricating an integrated circuit, comprising the steps of: (a) generating a circuit layout of said integrated circuit, comprising the substeps of: (a1) determining a surface area of a layer of metallization used in said circuit; (a2) comparing said surface area with a first predetermined value; if said area is less than said first predetermined value, proceeding with the following series of steps; (a3) initializing a mesh pattern of local wires with physical wires; (a4) removing an overlap between said local and said physical wires; (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires; (a6) removing segments of said local wires of a length less than a second predetermined value; (a7) creating a boundary of a second predetermined distance surrounding said physical wires; and (a8) removing segments of said local wires which are outside said boundary; (b) forming active regions on an integrated circuit chip; (c) forming a metallization layer on the chip; (d) forming a photoresist layer on the metallization layer; (e) imaging the photoresist layer in accordance with said circuit layout; (f) developing the photoresist layer; (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (h) removing the photoresist layer.
Claim 10
Independent Claim
213 words
A method of fabricating an integrated circuit, comprising the steps of: (a) generating a circuit layout of said integrated circuit, comprising the substeps of: (a1) determining a surface area of a layer of metallization used in said circuit; (a2) comparing said surface area with a first predetermined value; if said area is less than said first predetermined value, proceeding with the following series of steps; (a3) initializing a mesh pattern of local wires with physical wires; (a4) removing an overlap between said local and said physical wires; (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires; (a6) removing segments of said local wires of a length less than a second predetermined value; (a7) creating a boundary of a second predetermined distance surrounding said physical wires; and (a8) removing segments of said local wires which are outside said boundary; (b) forming active regions on an integrated circuit chip; (c) forming a metallization layer on the chip; (d) forming a photoresist layer on the metallization layer; (e) imaging the photoresist layer in accordance with said circuit layout; (f) developing the photoresist layer; (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (h) removing the photoresist layer.
Claim 11
Dependent Claim
49 words
A method as in claim 7, in which step (a) further comprises the substeps of: (a9) changing the characterization of said local wires causing said local wires to appear as physical wires; and (a10) repeating steps (a1) through (a8) until said area is greater than said first predetermined value.
Claim 12
Dependent Claim
31 words
A method as in claim 8, in which step (a) further comprises the substep of: (a11) distinguishing said local wires from said physical wires; wherein step (a11) follows said step (a8).
Claim 13
Independent Claim
168 words
A method of forming metallization on an integrated circuit, comprising the steps of: (a) generating a circuit layout of said integrated circuit, comprising the substeps of: (a1) determining a surface area of metallization used in said circuit layout; (a2) comparing said surface area with a first predetermined value; (a3) determining a distance between a first working line and a second working line to determine if said first or said second working line is a lonely line; (a4) comparing said distance to a second predetermined value; and if said distance is greater than said second predetermined value, (a5) placing a dummy line at a predetermined distance from said lonely line; (b) forming a metallization layer on an integrated circuit chip; (c) forming a photoresist layer on the metallization layer; (d) imaging the photoresist layer in accordance with said circuit layout; (e) developing the photoresist layer; (f) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (g) removing the photoresist layer.
Claim 14
Independent Claim
168 words
A method of forming metallization on an integrated circuit, comprising the steps of: (a) generating a circuit layout of said integrated circuit, comprising the substeps of: (a1) determining a surface area of metallization used in said circuit layout; (a2) comparing said surface area with a first predetermined value; (a3) determining a distance between a first working line and a second working line to determine if said first or said second working line is a lonely line; (a4) comparing said distance to a second predetermined value; and if said distance is greater than said second predetermined value, (a5) placing a dummy line at a predetermined distance from said lonely line; (b) forming a metallization layer on an integrated circuit chip; (c) forming a photoresist layer on the metallization layer; (d) imaging the photoresist layer in accordance with said circuit layout; (e) developing the photoresist layer; (f) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (g) removing the photoresist layer.
Claim 15
Dependent Claim
31 words
A method as in claim 10, in which step (a) further comprises the substep of: (a6) repeating steps (a1) through (a5) until said area is at least said first predetermined value.
Claim 16
Dependent Claim
30 words
A method as in claim 11, in which step (a) further comprises the substep of: (a7) distinguishing said dummy line from said working line; wherein step (a7) follows step (a3).
Claim 17
Independent Claim
202 words
A method of forming metallization on an integrated circuit, comprising the steps of: (a) generating a circuit layout using a computer, comprising the substeps of: (a1) determining a surface area of said metallization; (a2) comparing said area with a first predetermined value; if said area is less than said first predetermined value, said computer proceeding with the following series of substeps; (a3) initializing a mesh pattern of local wires with physical wires; (a4) removing an overlap between said local and said physical wires; (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires; (a6) removing segments of said local wires of a length less than a second predetermined value; (a7) creating a boundary of a second predetermined distance surrounding said physical wires; and (a8) removing segments of said local wires which are outside said boundary; (b) forming a metallization layer on an integrated circuit chip; (d) forming a photoresist layer on the metallization layer; (e) imaging the photoresist layer in accordance with said circuit layout; (f) developing the photoresist layer; (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (h) removing the photoresist layer.
Claim 18
Independent Claim
202 words
A method of forming metallization on an integrated circuit, comprising the steps of: (a) generating a circuit layout using a computer, comprising the substeps of: (a1) determining a surface area of said metallization; (a2) comparing said area with a first predetermined value; if said area is less than said first predetermined value, said computer proceeding with the following series of substeps; (a3) initializing a mesh pattern of local wires with physical wires; (a4) removing an overlap between said local and said physical wires; (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires; (a6) removing segments of said local wires of a length less than a second predetermined value; (a7) creating a boundary of a second predetermined distance surrounding said physical wires; and (a8) removing segments of said local wires which are outside said boundary; (b) forming a metallization layer on an integrated circuit chip; (d) forming a photoresist layer on the metallization layer; (e) imaging the photoresist layer in accordance with said circuit layout; (f) developing the photoresist layer; (g) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (h) removing the photoresist layer.
Claim 19
Dependent Claim
49 words
A method as in claim 13, in which step (a) further comprises the substeps of: (a9) changing the characterization of said local wires causing said local wires to appear as physical wires; and (a10) repeating steps (a1) through (a8) until said area is greater than said first predetermined value.
Claim 20
Dependent Claim
31 words
A method as in claim 14, in which step (a) further comprises the substep of: (a11) distinguishing said local wires from said physical wires; wherein step (a11) follows said step (a8).
Claim 21
Independent Claim
206 words
A method of forming metallization on an integrated circuit, comprising the steps of: (a) generating a circuit layout of said integrated circuit, comprising the substeps of: (a1) determining a surface area of a layer of metallization used in said circuit; (a2) comparing said surface area with a first predetermined value; if said area is less than said first predetermined value, proceeding with the following series of steps; (a3) initializing a mesh pattern of local wires with physical wires; (a4) removing an overlap between said local and said physical wires; (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires; (a6) removing segments of said local wires of a length less than a second predetermined value; (a7) creating a boundary of a second predetermined distance surrounding said physical wires; and (a8) removing segments of said local wires which are outside said boundary; (b) forming a metallization layer over the chip; (c) forming a photoresist layer over the metallization layer; (d) imaging the photoresist layer in accordance with said circuit layout; (e) developing the photoresist layer; (f) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (g) removing the photoresist layer.
Claim 22
Independent Claim
206 words
A method of forming metallization on an integrated circuit, comprising the steps of: (a) generating a circuit layout of said integrated circuit, comprising the substeps of: (a1) determining a surface area of a layer of metallization used in said circuit; (a2) comparing said surface area with a first predetermined value; if said area is less than said first predetermined value, proceeding with the following series of steps; (a3) initializing a mesh pattern of local wires with physical wires; (a4) removing an overlap between said local and said physical wires; (a5) removing portions of said local wires which are within a first predetermined distance from said physical wires; (a6) removing segments of said local wires of a length less than a second predetermined value; (a7) creating a boundary of a second predetermined distance surrounding said physical wires; and (a8) removing segments of said local wires which are outside said boundary; (b) forming a metallization layer over the chip; (c) forming a photoresist layer over the metallization layer; (d) imaging the photoresist layer in accordance with said circuit layout; (e) developing the photoresist layer; (f) etching the metallization layer using the photoresist layer as developed in step (e) as an etch mask; and (g) removing the photoresist layer.
Claim 23
Dependent Claim
49 words
A method as in claim 16, in which step (a) further comprises the substeps of: (a9) changing the characterization of said local wires causing said local wires to appear as physical wires; and (a10) repeating steps (a1) through (a8) until said area is greater than said first predetermined value.
Claim 24
Dependent Claim
31 words
A method as in claim 17, in which step (a) further comprises the substep of: (a11) distinguishing said local wires from said physical wires; wherein step (a11) follows said step (a8).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |