Patent US5475829A successfully refreshed from Google Patents.
US5475829A
Expired / Lapsed
US
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Computer system which overrides write protection status during execution in system management mode
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-03-22
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Granted: 1995-12-12
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Expires: 2013-03-22
Abstract
Abstract A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices at their desired optimal speeds. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller operates in system management mode to override any write protect status of memory so that the SMRAM can be located in the main memory space and be write protected during normal operations but be full usable during system management mode.
Inventors
- 👤 Gary W. Thome
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:11
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1615; G06F12/00; G06F12/14; G06F12/1458; G06F12/1491
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
96 words
A method for operating a computer system having several operating modes, the operating modes including a system management mode and being operable in the main memory space of the computer, each of the operating modes providing identical bus cycles for accessing the main memory space, the method comprising the steps of: providing an indication that a portion of the main memory space is write protected; determining when system management mode is active; and overriding said indication of write protection when system management mode is determined to be active, so that the main memory space is writable.
Claim 2
Independent Claim
96 words
A method for operating a computer system having several operating modes, the operating modes including a system management mode and being operable in the main memory space of the computer, each of the operating modes providing identical bus cycles for accessing the main memory space, the method comprising the steps of: providing an indication that a portion of the main memory space is write protected; determining when system management mode is active; and overriding said indication of write protection when system management mode is determined to be active, so that the main memory space is writable.
Claim 3
Dependent Claim
120 words
The method of claim 1, further comprising the steps of: performing write operations to main memory and returning an operation complete signal when the write protect indication is not provided; and returning only said operation complete signal when the write protect indication is provided without performing a write operation to main memory, and wherein said step of overriding causes said step of performing write operations to write to main memory and return an operation complete signal when the write protect indication is provided and system management mode is determined to be active and said step of returning only said operation complete signal when the write protect indication is provided without performing a write operation to main memory to be defeated.
Claim 4
Dependent Claim
96 words
A computer system having several operating modes, the operating modes including a system management mode and being operable in the main memory space of the computer, each of the operating modes providing identical bus cycles for accessing the main memory space, the computer system comprising: means for providing an indication that a portion of the main memory space is write protected; means for determining when system management mode is active; and means for overriding said indication of write protection when system management mode is determined to be active, so that the main memory space is writable.
Claim 5
Dependent Claim
96 words
A computer system having several operating modes, the operating modes including a system management mode and being operable in the main memory space of the computer, each of the operating modes providing identical bus cycles for accessing the main memory space, the computer system comprising: means for providing an indication that a portion of the main memory space is write protected; means for determining when system management mode is active; and means for overriding said indication of write protection when system management mode is determined to be active, so that the main memory space is writable.
Claim 6
Dependent Claim
145 words
The computer system of claim 3, wherein the computer system utilizes an operation complete signal after completion of a memory operation, the computer system further comprising: means for performing write operations to main memory and returning an operation complete signal when the write protect indication is not provided; and means for returning only said operation complete signal when the write protect indication is provided without performing a write operation to main memory, and wherein said means for overriding causes said means for performing write operations to write to main memory and return an operation complete signal when the write protect indication is provided and system management mode is determined to be active and said means for overriding causes said means for returning only said operation complete signal when the write protect indication is provided without performing a write operation to main memory to be defeated.
Claim 7
Dependent Claim
253 words
A computer system comprising: a memory; a processor having a system management mode and performing write operations to said memory during both system management mode and in modes other than system management mode, providing an indication that system management mode is active and receiving an operation complete indication to proceed to the next operation; means for providing an indication that a portion of the memory is write protected; a memory controller coupled to said processor, to said memory and to said means for indication write protection for controlling operations of said memory, wherein said memory controller includes: means for determining when system management mode is active; means for overriding said indication of write protection when system management mode is determined to be active; means for performing write operations to said memory and returning an operation complete signal to said processor when the write protect indication is not provided; and means for returning only said operation complete signal to said processor when the write protect indication is provided without performing a write operation to said memory, and wherein said means for overriding causes said means for performing write operations to write to said memory and return an operation complete signal to said processor when the write protect indication is provided and system management mode is determined to be active and said means for overriding causes said means for returning only said operation complete signal to said processor when the write protect indication is provided without performing a write operation to memory to be defeated.
Claim 8
Dependent Claim
253 words
A computer system comprising: a memory; a processor having a system management mode and performing write operations to said memory during both system management mode and in modes other than system management mode, providing an indication that system management mode is active and receiving an operation complete indication to proceed to the next operation; means for providing an indication that a portion of the memory is write protected; a memory controller coupled to said processor, to said memory and to said means for indication write protection for controlling operations of said memory, wherein said memory controller includes: means for determining when system management mode is active; means for overriding said indication of write protection when system management mode is determined to be active; means for performing write operations to said memory and returning an operation complete signal to said processor when the write protect indication is not provided; and means for returning only said operation complete signal to said processor when the write protect indication is provided without performing a write operation to said memory, and wherein said means for overriding causes said means for performing write operations to write to said memory and return an operation complete signal to said processor when the write protect indication is provided and system management mode is determined to be active and said means for overriding causes said means for returning only said operation complete signal to said processor when the write protect indication is provided without performing a write operation to memory to be defeated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-11 | 1999-06-12 | 1999-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-11 | 2003-06-12 | 2003-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-11 | 2007-06-12 | 2007-12-12 | $7700.00 | Window Closed / Lapsed |