US5475690A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay compensated signal propagation
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-11-10
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Granted: 1995-12-12
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Expires: 2014-11-10
Abstract
Abstract In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays experienced by the digital signals are measured as a delay value relative to a reference clock signal propagated through a second signaling path duplicating the delays of the first signaling path. The delay value is used to selectively delay the digital signal to maintain a fixed relationship between the transmitted and received digital signals. Delay measuring and regulation is provided by driving the reference and digital signals through comparable tapped delay lines, the output taps of a measuring delay line controlling the output taps of a delaying line. Storage latches are provide to hold the measured delay value stable between successive samples.
Inventors
- 👤 Douglas J. Burns
- 👤 David M. Fenwick
- 👤 Ricky C. Hetherington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:38
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
227 words
An apparatus for controlling propagation of digital signals in a computer system, comprising: means for transmitting digital signals; means, connected to the means for transmitting, for propagating the digital signals, the means for propagating the digital signals delaying the digital signals an intrinsic amount of time, the intrinsic amount of time being uncontrollable over time; means for receiving the digital signals from the means for propagating; means for generating a first clock signal to maintain a fixed-time relationship between when the digital signals are transmitted and received; means for generating a second clock signal; means for propagating the second clock signal, the means for propagating the second clock signal delaying the second clock signal an equivalent intrinsic amount of time as the digital signals are delayed; means for measuring the equivalent intrinsic amount of time the second clock signal is delayed; means for determining a delay time, the delay time being a difference between a predetermined maximum amount of time the digital signals are delayed by the means for propagating the digital signals and the equivalent intrinsic amount of time the second clock signal is delayed; and means for delaying the digital signals by the delay time to reduce variations between the fixed-time relationship when the digital signals are transmitted and received, wherein the first clock rate is to be increased without overlapping successively received digital signals.
Claim 2
Independent Claim
227 words
An apparatus for controlling propagation of digital signals in a computer system, comprising: means for transmitting digital signals; means, connected to the means for transmitting, for propagating the digital signals, the means for propagating the digital signals delaying the digital signals an intrinsic amount of time, the intrinsic amount of time being uncontrollable over time; means for receiving the digital signals from the means for propagating; means for generating a first clock signal to maintain a fixed-time relationship between when the digital signals are transmitted and received; means for generating a second clock signal; means for propagating the second clock signal, the means for propagating the second clock signal delaying the second clock signal an equivalent intrinsic amount of time as the digital signals are delayed; means for measuring the equivalent intrinsic amount of time the second clock signal is delayed; means for determining a delay time, the delay time being a difference between a predetermined maximum amount of time the digital signals are delayed by the means for propagating the digital signals and the equivalent intrinsic amount of time the second clock signal is delayed; and means for delaying the digital signals by the delay time to reduce variations between the fixed-time relationship when the digital signals are transmitted and received, wherein the first clock rate is to be increased without overlapping successively received digital signals.
Claim 3
Dependent Claim
39 words
The apparatus as in claim 1 wherein the means for propagating the second clock signal includes a delay circuit, the operation of the delay circuit being substantially equivalent to the operation of the means for propagating the digital signals.
Claim 4
Dependent Claim
32 words
The apparatus as in claim 2 wherein the means for propagating the digital signals includes an address buffer connected to the means for transmitting and a cache memory of the computer system.
Claim 5
Dependent Claim
37 words
The apparatus as in claim 1 wherein the means for propagating the second clock signal includes a first delay line measuring the delay of the second clock signal, and a second delay line delaying the digital signals.
Claim 6
Dependent Claim
42 words
The apparatus as in claim 4 further including a latch having inputs connected to the first delay line, the latch storing the delay time, and a multiplexer connected to the latch and the second delay line, the multiplexer receiving the delay time.
Claim 7
Independent Claim
216 words
An apparatus for controlling propagation of digital signals in a computer system, comprising: means for propagating a digital signal, the means for propagating having an intrinsic delay uncontrollable over time; means for measuring a difference in time of a predetermined maximum delay and the intrinsic delay experienced by the digital signal while the digital signal is propagated by the means for propagating at a particular time; and means for delaying the digital signal by the difference in time to increase a rate at which the digital signal can be propagated a first clock, connected to the means for propagating, the first clock determining the rate at which the digital signal can be propagated; a reference clock, connected to the means for measuring, the reference clock generating a reference signal; a first delay line substantially duplicating the operation of the means for propagating, the first delay line propagating the reference signal while the digital signal is propagated; a latch coupled to the first delay line for storing a value representative of the difference of a predetermined maximum delay and the intrinsic delay experienced by the digital signal while the digital signal is propagated at a particular time; and a multiplexer connected to the latch and a second delay line for delaying the digital signal by the difference.
Claim 8
Independent Claim
216 words
An apparatus for controlling propagation of digital signals in a computer system, comprising: means for propagating a digital signal, the means for propagating having an intrinsic delay uncontrollable over time; means for measuring a difference in time of a predetermined maximum delay and the intrinsic delay experienced by the digital signal while the digital signal is propagated by the means for propagating at a particular time; and means for delaying the digital signal by the difference in time to increase a rate at which the digital signal can be propagated a first clock, connected to the means for propagating, the first clock determining the rate at which the digital signal can be propagated; a reference clock, connected to the means for measuring, the reference clock generating a reference signal; a first delay line substantially duplicating the operation of the means for propagating, the first delay line propagating the reference signal while the digital signal is propagated; a latch coupled to the first delay line for storing a value representative of the difference of a predetermined maximum delay and the intrinsic delay experienced by the digital signal while the digital signal is propagated at a particular time; and a multiplexer connected to the latch and a second delay line for delaying the digital signal by the difference.
Claim 9
Dependent Claim
122 words
In a computer system, an apparatus for controlling propagation of digital signals, the computer system including a central processing unit, and a memory, comprising: an address buffer transmitting address signals from the central processor to the memory, the address buffer delaying the address signals while transmitting; means for maintaining a fixed rate at which the address signals are transmitted; means for determining a delay time, the delay time being a difference between a predetermined maximum time the address buffer can delay the address signals and a measured amount of time the address signals are delayed by the address buffer; and means for delaying the address signals by the delay time to increase the fixed rate at which the address signals are transmitted.
Claim 10
Dependent Claim
122 words
In a computer system, an apparatus for controlling propagation of digital signals, the computer system including a central processing unit, and a memory, comprising: an address buffer transmitting address signals from the central processor to the memory, the address buffer delaying the address signals while transmitting; means for maintaining a fixed rate at which the address signals are transmitted; means for determining a delay time, the delay time being a difference between a predetermined maximum time the address buffer can delay the address signals and a measured amount of time the address signals are delayed by the address buffer; and means for delaying the address signals by the delay time to increase the fixed rate at which the address signals are transmitted.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-11 | 1999-06-12 | 1999-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-11 | 2003-06-12 | 2003-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-11 | 2007-06-12 | 2007-12-12 | $7700.00 | Window Closed / Lapsed |