Data communication circuit

Claim 1

Data communication circuit comprising at least one slave device, a master device for controlling the operation of said slave device, and a two-wire bus connectable between said master device and said slave device for passing digital information therebetween, said master device creating a potential difference (V(t)) between said two wires so as to provide power to said slave device, said master device comprising pulse creating means for creating pulses in said potential difference (V(t)), said pulse creating means comprising means for creating a first data pulse having an amplitude less than a first predetermined value, and a second data pulse having an amplitude greater than said first predetermined value, said first data pulse being in one of a logically low or a logically high state and said second data pulse being in a logically low or a logically high state different from the state of said first data pulse, said slave device comprising pulse decoding means for detecting said pulses and producing a synchronization signal (Clk) upon the detection of each said pulse, characterized in that said master device further comprises pulse control means for causing said pulse creating means to create a series of said data pulses having the same state when said digital information is read from said slave device, and said slave device further comprises means to change the state of selected ones of data pulses in said series in response to the digital information to be read.