EP0110179A2
Expired / Lapsed
EP
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Multi-level transfer circuitry for transmitting digital signals between integrated circuits
Assignee: International Business Machines Corp
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Filing: 1983-11-03
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Granted: —
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Expires: 2003-11-03
Abstract
Abstract Transfer circuitry is disclosed for transmitting multi-bit digital signals (X,, Y i ) from one integrated circuit to another upon a single conductor (48) utilizing a multi-level analog signal. The transmitting circuitry (2) includes first through third drivers (10, 20, 30), only one of which is activated at any one time. The collector of an output transistor of a first of the drivers is coupled directly to the single bus conductor (48), the collector of an output transistor of the second driver is coupled to the bus through a single transistor, and the collector of an output transistor of the third driver is coupled to the bus through two series-connected diodes. The receiving circuitry (3) is composed of three receivers (50, 60, 80), each including an input and output transistor pair coupled in a Darlington configuration. The base of the input transistor of the first receiver is coupled to the bus (48) through a single diode connected in a first direction, the second receiver coupled to the input bus through a diode in a direction opposite the first direction, and the third receiver is coupled to the input bus via two series-connected diodes, this arrangement of diodes providing three different threshold voltage levels. The outputs of the three receivers are combined to yield an output digital signal (X o , Y o ) which corresponds to the input digital signal.
Inventors
- 👤 Haluk O. Askin
- 👤 Bryant K. Ho
- 👤 Guy Rabbat
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01825
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
189 words
Transfer circuitry for transmitting a multi-bit digital signal between transmitting and receiving locations over a single conductor, characterized by transmitting means (2) at said transmitting location for producing a multi-level signal upon said conductor (48) having a level determined in accordance with a state of an input multi-bit (X i , Y i ) digital signal, said transmitting means comprising a plurality of first transistors (18, 29, 37) and first diodes (19, 39, 40) coupled such that the levels of said multi-level signal are determined by saturation voltages of said first transistors and forward drops of said first diodes; and receiving means (3) at said receiving location for producing an output multi-bit (X , Y o ) digital signal in response to said multi-level signal and corresponding to said input multi-bit digital signal, said receiving means comprising a plurality of second transistors (55, 58, 65, 68, 86, 88) and second diodes (51, 61, 81, 82) coupled to detect said multi-level signal in accordance with a plurality of threshold levels, said threshold levels being determined by threshold voltage levels of said second transistors and forward drops of said second diodes.
Claim 2
Dependent Claim
189 words
Transfer circuitry for transmitting a multi-bit digital signal between transmitting and receiving locations over a single conductor, characterized by transmitting means (2) at said transmitting location for producing a multi-level signal upon said conductor (48) having a level determined in accordance with a state of an input multi-bit (X i , Y i ) digital signal, said transmitting means comprising a plurality of first transistors (18, 29, 37) and first diodes (19, 39, 40) coupled such that the levels of said multi-level signal are determined by saturation voltages of said first transistors and forward drops of said first diodes; and receiving means (3) at said receiving location for producing an output multi-bit (X , Y o ) digital signal in response to said multi-level signal and corresponding to said input multi-bit digital signal, said receiving means comprising a plurality of second transistors (55, 58, 65, 68, 86, 88) and second diodes (51, 61, 81, 82) coupled to detect said multi-level signal in accordance with a plurality of threshold levels, said threshold levels being determined by threshold voltage levels of said second transistors and forward drops of said second diodes.
Claim 3
Dependent Claim
122 words
The transfer circuitry of claim 1, characterized in that said transmitting means (2).comprises a plurality of drivers (10, 20, 30), each of said drivers comprising an input transistor (15, 26, 35) and an output transistor (18, 29, 37) driven by said input transistor, a first one of said drivers (20) having an output transistor (29) having an output electrode coupled directly to said conductor (48), a second one of said drivers (10) having an output transistor (18) having an output electrode coupled through a single one (19) of said first diodes to said conductor, and a third of said drivers (30) having an output transistor (37) having an output electrode coupled through two (39, 40) of said first diodes to said conductor.
Claim 4
Dependent Claim
25 words
The transfer circuitry of claim 2, characterized in that at most one of said driver circuit (10, 20, 30) is active at any one time.
Claim 5
Dependent Claim
74 words
The transfer circuitry of claim 2, characterized in that said input multi-bit digital signal is a two-bit (X., Y i ) signal, said first (20) and second (10) drivers being coupled to operate in response to a first bit (X i ) of said input multi-bit digital signal and said first (20) and third (30) drivers being coupled to be operated in response to a second bit (Y.) of said input multi-bit digital signal.
Claim 6
Dependent Claim
77 words
The transfer circuitry of claim 2, characterized in that said receiving means (3) comprises a plurality of receiver circuits (50, 60, 80), each of said receiver circuits comprising at least one transistor (55, 65, 86) having a control electrode connected in series with at least one of said second diodes (51, 61, 81, 82), each of said diodes of each of said receivers having one electrode coupled to receive said multi-level signal (X., Y i ) .
Claim 7
Dependent Claim
42 words
The transfer circuitry of claim 5-, further comprising means (58, 68, 71, 88) for combining outputs of said transistors (55, 65, 86) of each of said receiver circuits (50, 60, 80) to produce said output multi-bit digital signal (Y , Y ).
Claim 8
Dependent Claim
162 words
The transfer circuitry of claim 5, characterized in said receiving means (3) comprises first through third receiver circuits (50, 60, 80), each of said receiver circuits comprising an input transistor (55, 65, 86) and an output transistor (58, 68, 88) coupled to be driven by said input transistor, said first receiver (50) comprising one (51) of said second diodes having a cathode coupled to said single conductor (48) and an anode coupled to an input electrode of the input transistor (55) of said first receiver, said second receiver (60) comprising one (61) of said second diodes having an anode,coupled to said single conductor and a cathode coupled to an input electrode of the input transistor (65) of said second receiver, and said third receiver (80) comprising a series connection of two (81, 82) of said second diodes having a cathode coupled to said single conductor and an anode coupled to an input electrode of the input transistor (86) of said third receiver.
Claim 9
Dependent Claim
32 words
The transfer circuitry of claim 7, wherein the input (55, 65, 86) and output (58, 68, 88) transistors of each of said receivers (50, 60, 80) are coupled in a Darlington configuration.
References Cited (Backward Citations)
No citation records indexed.
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