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US5473565A
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Method of flash writing with small operation current and semiconductor memory circuit according to the method
Assignee: NEC Electronics Corp
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Filing: 1994-09-02
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Granted: 1995-12-05
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Expires: 2014-09-02
Abstract
Abstract The present invention provides a semiconductor memory circuit which can restrict the increase of an operation current in a flash write mode to a minimum even when there are problems caused in the manufacturing process such as short-circuits in the wiring. A timing control circuit of the semiconductor memory circuit of the present invention comprises an FW latch signal generation circuit and a latch circuit both for detecting that a row address strobe signal, an RAS signal and a flash write enable signal inputted have become active, and an FW gate signal generation circuit for activating the FW gate signal for only a limited fixed time determined by a delay circuit when an FW gate activation signal is outputted from the latch circuit which has detected the activation of both signals. With the FW gate signal activated, the flash write gate switch turns active for performing the flash write activity. After the flash write activity is finished, the FW gate signal becomes inactive immediately even when the RAS signal is active.
Inventors
- 👤 Takashi Kusakari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:59
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20; G11C7/06; G11C7/10; G11C7/1078; G11C7/22
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
194 words
A method of flash writing for a semiconductor memory circuit, wherein said memory circuit includes: a plurality of memory cells, with each cell being disposed at a crossing area of one of a plurality of word lines and one of a plurality of bit lines; a plurality of sense amplifiers arranged such that one sense amplifier amplifies data of each of said pairs of bit lines; a flash write data bus to be supplied with flash write data; and a plurality of flash write gate switches for switching connections with said flash write data bus between the bit lines in said pairs of bit lines; said method comprising the steps of: activating a word line corresponding to a given row address, activating said plurality of flash write gate switches, activating said plurality of sense amplifiers, and writing said flash write data to all memory cells connected to said activated word line simultaneously; and controlling the length of a time period during which said flash write gate switches are activated by said control means such that said flash write gate switches are activated only during a time period in which said word line is activated.
Claim 2
Independent Claim
194 words
A method of flash writing for a semiconductor memory circuit, wherein said memory circuit includes: a plurality of memory cells, with each cell being disposed at a crossing area of one of a plurality of word lines and one of a plurality of bit lines; a plurality of sense amplifiers arranged such that one sense amplifier amplifies data of each of said pairs of bit lines; a flash write data bus to be supplied with flash write data; and a plurality of flash write gate switches for switching connections with said flash write data bus between the bit lines in said pairs of bit lines; said method comprising the steps of: activating a word line corresponding to a given row address, activating said plurality of flash write gate switches, activating said plurality of sense amplifiers, and writing said flash write data to all memory cells connected to said activated word line simultaneously; and controlling the length of a time period during which said flash write gate switches are activated by said control means such that said flash write gate switches are activated only during a time period in which said word line is activated.
Claim 3
Dependent Claim
54 words
The method of flash writing according to claim 1 wherein: the length of said time period during which said flash write gate switches are activated is controlled so as to be as short in duration as possible while still long enough in duration to allow for writing flash write data to said bit line.
Claim 4
Dependent Claim
179 words
A semiconductor memory circuit comprising: a plurality of memory cells, with each cell being disposed at a crossing area of one of a plurality of word lines and one of a plurality of bit lines; a plurality of sense amplifiers arranged such that one sense amplifier amplifies data of each of said pairs of bit lines; a flash write data bus that is supplied with flash write data; a plurality of flash write gate switches for switching connection with said flash write data bus between the bit lines of said pairs of bit lines; a control means for activating a word line corresponding to a given row address, activating said flash write gate switches, activating said sense amplifiers and writing flash write data to memory cells connected to an activated word line; and a timing control circuit for controlling the length of a time period during which said flash write gate switches are activated by said control means such that said flash write gate switches are activated only during a time period in which said word line is activated.
Claim 5
Dependent Claim
179 words
A semiconductor memory circuit comprising: a plurality of memory cells, with each cell being disposed at a crossing area of one of a plurality of word lines and one of a plurality of bit lines; a plurality of sense amplifiers arranged such that one sense amplifier amplifies data of each of said pairs of bit lines; a flash write data bus that is supplied with flash write data; a plurality of flash write gate switches for switching connection with said flash write data bus between the bit lines of said pairs of bit lines; a control means for activating a word line corresponding to a given row address, activating said flash write gate switches, activating said sense amplifiers and writing flash write data to memory cells connected to an activated word line; and a timing control circuit for controlling the length of a time period during which said flash write gate switches are activated by said control means such that said flash write gate switches are activated only during a time period in which said word line is activated.
Claim 6
Dependent Claim
65 words
The semiconductor memory circuit according to claim 3 wherein said timing control circuit further comprises: an activation detecting circuit for detecting that an inputted row address strobe signal and flash write enable signal are active; and an activation time adjusting circuit for activating said flash write gate switch for a predetermined time period when said activation detecting circuit detects that said inputted signals are active.
Claim 7
Dependent Claim
58 words
The semiconductor memory circuit according to claim 4 wherein the length of said time period in which said flash write gate switch is activated by said timing control circuit is controlled so as to be as short in duration as possible while still long enough in duration to allow for writing flash write data to said bit lines.
Claim 8
Dependent Claim
58 words
The semiconductor memory circuit according to claim 3 wherein the length of said time period in which said flash write gate switch is activated by said timing control circuit is controlled so as to be as short in duration as possible while still long enough in duration to allow for writing flash write data to said bit lines.
Claim 9
Dependent Claim
23 words
The semiconductor memory circuit according to claim 3 wherein a plurality of said memory cells are disposed in the form of an array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |