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US5473267A
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Programmable logic device with memory that can store routing data of logic data
Assignee: STMicroelectronics Ltd Great Britain
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Filing: 1995-02-03
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Granted: 1995-12-05
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Expires: 2015-02-03
Abstract
Abstract A programmable logic device is disclosed which can be used either as a look-up table logic device or as a logic function generator. This enables combinations to be provided such as the combination of a look-up table with a fixed gate field programmable gate array.
Inventors
- 👤 Anthony I. Stansfield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/1778; H03K19/17796; G; G11; G11C; G11C15/00; G11C15/04; H03K19/17704
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
131 words
A programmable logic device comprising: a plurality of logic elements and connected to each logic element a switch circuit the state of which is controllable to determine connections between the logic elements; a storage circuit providing at least one storage location and operatively connected to the switch circuit; addressing circuitry operatively connected to a plurality of said storage locations whereby a selected one of said storage locations can be addressed, wherein each storage location can be programmed to hold in mode (a) routing data defining the state of its associated switch circuit or in mode (b) logic data representing the result of a logic function and which is output from a selectively addressed storage location; and programming circuitry operable to determine whether the storage circuits implement mode (a) or mode (b).
Claim 2
Dependent Claim
131 words
A programmable logic device comprising: a plurality of logic elements and connected to each logic element a switch circuit the state of which is controllable to determine connections between the logic elements; a storage circuit providing at least one storage location and operatively connected to the switch circuit; addressing circuitry operatively connected to a plurality of said storage locations whereby a selected one of said storage locations can be addressed, wherein each storage location can be programmed to hold in mode (a) routing data defining the state of its associated switch circuit or in mode (b) logic data representing the result of a logic function and which is output from a selectively addressed storage location; and programming circuitry operable to determine whether the storage circuits implement mode (a) or mode (b).
Claim 3
Dependent Claim
44 words
A programmable logic device as claimed in claim 1, wherein each logic element comprises a logic gate and each switch circuit comprises a selection circuit for selectively connecting from a set of input signals an input signal to an input of said logic gate.
Claim 4
Dependent Claim
26 words
A programmable logic device as claimed in claim 2, wherein each logic gate has a plurality of inputs, with a selection circuit associated with each input.
Claim 5
Dependent Claim
47 words
A programmable logic device as claimed in claim 2 or 3, wherein each logic gate has an output, the outputs of selected logic gates being connected to supply some or all of said set of input signals to the selection circuits of others of said logic gates.
Claim 6
Dependent Claim
26 words
A programmable logic device as claimed in claim 2, wherein each selection circuit comprises a multiplexer controllable by a data bit stored in said storage location.
Claim 7
Dependent Claim
45 words
A programmable logic device as claimed in claim 1, wherein each logic element is selectively connectable via said switch circuit to an output line of the device, the logic elements being arranged in sets and each set being selectively connectable to a common output line.
Claim 8
Dependent Claim
35 words
A programmable logic device as claimed in claim 6, wherein each logic element is a transistor having its gate connected to receive an input signals and its source/drain path selectively connectable to said output line.
References Cited (Backward Citations)
US4646271B1
Cited
US4646271A
Cited
USRE34363E
Cited
US4831573A
Cited
JPH01125124A
Cited
US4876466A
Cited
US4896060A
Cited
US5243238A
Cited
US5214327A
Cited
US4975601A
Cited
US5051949A
Cited
US5282163A
Cited
US5414377A
Cited
US5299147A
Cited
US5381058A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |