System and method for executing branch instructions wherein branch target addresses are dynamically selectable under programmer control from writable branch address tables

Claim 1

A microsequencer bus controller for executing branch program instructions fetched from a read-only-memory control store comprising: a random-access-memory local store, said random-access-memory local store including: one or more branch address tables, each of said branch address tables including a plurality of branch target addresses pointing to instructions in the read-only-memory control store, wherein the size, location, and contents of said branch address tables may be changed by the execution of instructions fetched from the read-only-memory control store; a base address table, wherein said base address table has one or more entries, each one of said entries corresponding to one of said branch address tables, each one of said entries containing a base address of one of said branch address tables; and a mask/merge table, wherein said mask/merge table has one or more mask/merge entries, each one of said mask/merge entries containing a plurality of mask/merge flags; instruction decode means, coupled to the read-only-memory control store, for determining if an instruction fetched from the read-only-memory control store is a branch program instruction, and for extracting parameters specified by said branch program instruction, said parameters including a base pointer addressing one of said entries in said base address table and a mask/merge pointer addressing one of said mask/merge entries in said mask/merge table; a base address register to store said base address fetched from said entry in said base address table addressed by said base pointer; a mask/merge register to store said mask/merge flags fetched from said mask/merge entry in said mask/merge table addressed by said mask/merge pointer; an index register for receiving an index resulting from the execution of the previous instruction; mask logic, coupled to said instruction decode means, said base address register, and said mask/merge register, for masking selected bit pairs of said base address register according to the even-numbered bits of said mask/merge register to produce an intermediate indicator; merge logic, coupled to said mask logic, said index register, and said mask/merge register, for merging selected bit pairs of said intermediate indicator with selected bits of said index register according to the odd-numbered bits of said mask/merge register to produce an indicator into said selected branch address table where a selected branch target address is stored; and branch control logic, coupled to said merge logic, and said instruction decode means, for conditionally selecting the instruction addressed by either a next sequential address or said selected branch target address pointed to by said indicator as a next instruction to be fetched from the read-only-memory control store.

Claim 3

A method of transferring program control in a processor by executing a conditional branch program instruction fetched from a read-only-memory control store addressed by a program counter, the conditional branch program instruction having fields for storing a base pointer and a mask/merge pointer, the processor having loaded a register with an index during execution of the immediately preceding program instruction, the processor including a base address table for storing base addresses, a base register for holding a selected base address, a mask/merge table for storing a plurality of mask/merge flags, a mask/merge register for holding a selected plurality of mask/merge flags, and a plurality of branch address tables for storing branch target addresses, the base address table, mask/merge table and branch address tables being able to be modified by the processor executing program instructions programmed by a computer programmer, comprising the steps of: (a) determining if an instruction fetched from the read-only-memory control store is a conditional branch program instruction; (b) evaluating a branch condition specified by the instruction, when the instruction is a conditional branch program instruction; (c) selecting whether or not a branch is to be taken depending on the branch condition evaluation; (d) incrementing the program counter to address a next sequential instruction when the branch is not to be taken; (e) performing the following steps when the branch is to be taken: (e1) extracting the base pointer and the mask/merge pointer from the conditional branch program instruction, the base pointer addressing an entry in the base address table, the mask/merge pointer addressing a mask/merge entry in the mask/merge table; (e2) loading the base register with a base address of a branch address table containing branch target addresses, said base address being fetched from said entry in the base address table addressed by said base pointer; (e3) loading the mask/merge register with a plurality of mask/merge flags, said mask/merge flags being fetched from said mask/merge entry in the mask/merge table addressed by the mask/merge pointer; (e4) masking selected bits of said base address according to the even-numbered bits of said mask/merge flags to produce an intermediate indicator; (e5) merging selected bits of said intermediate indicator with selected bits of the index according to the odd-numbered bits of said mask/merge flags to produce an address of a branch address entry into said branch address table; and (e6) loading the program counter with a branch target address from said branch address entry into said branch address table.

Claim 4

A method of transferring program control in a processor by executing a conditional branch program instruction fetched from a read-only-memory control store addressed by a program counter, the conditional branch program instruction having fields for storing a base pointer and a mask/merge pointer, the processor having loaded a register with an index during execution of the immediately preceding program instruction, the processor including a base address table for storing base addresses, a base register for holding a selected base address, a mask/merge table for storing a plurality of mask/merge flags, a mask/merge register for holding a selected plurality of mask/merge flags, and a plurality of branch address tables for storing branch target addresses, the base address table, mask/merge table and branch address tables being able to be modified by the processor executing program instructions programmed by a computer programmer, comprising the steps of: (a) determining if an instruction fetched from the read-only-memory control store is a conditional branch program instruction; (b) evaluating a branch condition specified by the instruction, when the instruction is a conditional branch program instruction; (c) selecting whether or not a branch is to be taken depending on the branch condition evaluation; (d) incrementing the program counter to address a next sequential instruction when the branch is not to be taken; (e) performing the following steps when the branch is to be taken: (e1) extracting the base pointer and the mask/merge pointer from the conditional branch program instruction, the base pointer addressing an entry in the base address table, the mask/merge pointer addressing a mask/merge entry in the mask/merge table; (e2) loading the base register with a base address of a branch address table containing branch target addresses, said base address being fetched from said entry in the base address table addressed by said base pointer; (e3) loading the mask/merge register with a plurality of mask/merge flags, said mask/merge flags being fetched from said mask/merge entry in the mask/merge table addressed by the mask/merge pointer; (e4) masking selected bits of said base address according to the even-numbered bits of said mask/merge flags to produce an intermediate indicator; (e5) merging selected bits of said intermediate indicator with selected bits of the index according to the odd-numbered bits of said mask/merge flags to produce an address of a branch address entry into said branch address table; and (e6) loading the program counter with a branch target address from said branch address entry into said branch address table.