US4635188A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Means for fast instruction decoding for a computer
Assignee: HP Inc
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Filing: 1983-07-29
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Granted: 1987-01-06
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Expires: 2003-07-29
Abstract
Abstract A scheme for improving the decoding time of macroinstruction opcodes in a programmed computer is provided. By having a direct Instruction Jump Table responding to macroinstructions and a pipelined Address Jump Table responding to the same macroinstructions simultaneously, larger sequences of microinstructions are decoded in a minimum number of microcycles, thus resulting in a faster operating programmed computer.
Inventors
- 👤 Donald A. Williamson
- 👤 John F. Shelton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/22; G06F9/26; G06F9/262; G06F9/268; G06F9/3017; G06F9/38; G06F9/3885; G06F9/3889
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
97 words
An apparatus for fast instruction decoding in a computer comprising: a means for accessing a plurality of decoding means in response to a macroinstruction opcode; a first decoding means being accessed by said accessing means for providing a first level emulation instruction for execution in response to said macroinstruction opcode; a second decoding means being accessed simultaneously with the first decoding means by said accessing means for providing a microaddress code in response to said macroinstruction opcode; and a third decoding means for providing a second level emulation instruction for execution in response to said microaddress code.
Claim 2
Independent Claim
97 words
An apparatus for fast instruction decoding in a computer comprising: a means for accessing a plurality of decoding means in response to a macroinstruction opcode; a first decoding means being accessed by said accessing means for providing a first level emulation instruction for execution in response to said macroinstruction opcode; a second decoding means being accessed simultaneously with the first decoding means by said accessing means for providing a microaddress code in response to said macroinstruction opcode; and a third decoding means for providing a second level emulation instruction for execution in response to said microaddress code.
Claim 3
Dependent Claim
34 words
The apparatus as in claim 1 wherein said first and second decoding means operate in a first instruction cycle and said third decoding means operates in the next cycle immediately following said first cycle.
Claim 4
Dependent Claim
16 words
The apparatus as in claim 2 wherein said third decoding means is a control storage device.
Claim 5
Dependent Claim
23 words
The apparatus as in claim 2 wherein said second decoding means has a latch device as an input port for said macroinstruction opcode.
Claim 6
Dependent Claim
23 words
The apparatus as in claim 2 wherein said second decoding means has a register device as an output port for said microaddress code.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |