US5469561A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for controlling the running of a data processing apparatus
Assignee: Seiko Epson Corp
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Filing: 1992-12-22
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Granted: 1995-11-21
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Expires: 2012-12-22
Abstract
Abstract An apparatus and method for controlling the bus cycle running time of a data processing apparatus. The apparatus includes a CPU and at least one device such as a memory device, input/output device and the like which receives data from the C. A clock signal supplied to the CPU is varied based on the bus cycle or address within the device which is identified by the CPU for processing of the data. Alternatively, the frequency of the clock signal is varied based on ambient temperature and line voltage conditions. Accordingly, processing speed of the CPU can be varied to accommodate high speed memory devices and slower speed input/output devices.
Inventors
- 👤 Koji Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F1/00; G06F1/04; G06F1/08
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
171 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit is a predetermined type of bus cycle; producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of the bus cycle type; maintaining said at least one identifying signal in a constant logic state for a predetermined period; varying a frequency of the clock signal of the central processing unit based on the at least one identifying signal; and adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit; whereby the running time for processing data by the central processing unit is adjusted in accordance with the bus cycle type.
Claim 2
Independent Claim
171 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit is a predetermined type of bus cycle; producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of the bus cycle type; maintaining said at least one identifying signal in a constant logic state for a predetermined period; varying a frequency of the clock signal of the central processing unit based on the at least one identifying signal; and adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit; whereby the running time for processing data by the central processing unit is adjusted in accordance with the bus cycle type.
Claim 3
Dependent Claim
84 words
The method for controlling the running time of claim 1, wherein the bus cycles include a memory read bus cycle and a memory write bus cycle and further including producing a first clock signal having a first frequency based on the memory read bus cycle and a second clock signal having a second frequency based on the memory write bus cycle whereby the lengths of time for the central processing unit to read data from and write data into a memory device are different.
Claim 4
Independent Claim
79 words
A method for controlling the running time of different bus cycles of a central processing unit, comprising: processing data during the different bus cycles based on the frequency of a clock signal supplied to the central processing unit; and varying the frequency of the clock signal continuously based on line voltage which is supplied to the central processing unit; whereby the running time for processing data by the central processing unit is adjusted continuously in accordance with line voltage.
Claim 5
Independent Claim
79 words
A method for controlling the running time of different bus cycles of a central processing unit, comprising: processing data during the different bus cycles based on the frequency of a clock signal supplied to the central processing unit; and varying the frequency of the clock signal continuously based on line voltage which is supplied to the central processing unit; whereby the running time for processing data by the central processing unit is adjusted continuously in accordance with line voltage.
Claim 6
Dependent Claim
69 words
A data processing apparatus, comprising: CPU means for producing command signals corresponding to a bus cycle which the CPU means is presently operating under in response to a clock signal; and clock generating means for producing the clock signal and responsive to line voltage conditions for varying the frequency of the clock signal continuously; whereby the running time of the CPU means varies continuously based on line voltage conditions.
Claim 7
Dependent Claim
69 words
A data processing apparatus, comprising: CPU means for producing command signals corresponding to a bus cycle which the CPU means is presently operating under in response to a clock signal; and clock generating means for producing the clock signal and responsive to line voltage conditions for varying the frequency of the clock signal continuously; whereby the running time of the CPU means varies continuously based on line voltage conditions.
Claim 8
Independent Claim
204 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if said bus cycle controlled by said central processing unit is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by said central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of the bus cycle type and address; maintaining said at least one identifying signal in a constant logic state for a predetermined period; varying a frequency of said clock signal of the central processing unit based on the identifying signal; and adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit; whereby the running time for processing data by the central processing unit is adjusted in accordance with the bus cycle type and address.
Claim 9
Independent Claim
204 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if said bus cycle controlled by said central processing unit is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by said central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of the bus cycle type and address; maintaining said at least one identifying signal in a constant logic state for a predetermined period; varying a frequency of said clock signal of the central processing unit based on the identifying signal; and adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit; whereby the running time for processing data by the central processing unit is adjusted in accordance with the bus cycle type and address.
Claim 10
Dependent Claim
192 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle controlled by said central processing unit, said bus cycle including at least one clock cycle and involves bus access, determination means for determining, at or about the start of said bus cycle, if said bus cycle being processed by the central processing unit means is a predetermined type of bus cycle; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining means for maintaining said at least one identifying signal in a constant logic state for a predetermined period; frequency varying means for varying the frequency of the clock signal of the central processing unit based on the at least one identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit means; whereby the running time of the central processing unit means varies based on the bus cycle type.
Claim 11
Dependent Claim
192 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle controlled by said central processing unit, said bus cycle including at least one clock cycle and involves bus access, determination means for determining, at or about the start of said bus cycle, if said bus cycle being processed by the central processing unit means is a predetermined type of bus cycle; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining means for maintaining said at least one identifying signal in a constant logic state for a predetermined period; frequency varying means for varying the frequency of the clock signal of the central processing unit based on the at least one identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit means; whereby the running time of the central processing unit means varies based on the bus cycle type.
Claim 12
Dependent Claim
232 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle being controlled by said central processing unit, said bus cycle including at least one clock cycle and involves bus access; determination means for determining at or about the start of said bus cycle if said bus cycle being controlled by the central processing unit means is a predetermined type of bus cycle and determining at or about the start of said bus cycle whether an address that is accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of the bus cycle type and address; maintaining means for maintaining said at least one identifying signal in a constant logic state for a predetermined period; frequency varying means for varying the frequency of the clock signal of the central processing unit based on the at least one identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit; whereby the running time of the central processing unit means varies based on the bus cycle type and address.
Claim 13
Dependent Claim
232 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle being controlled by said central processing unit, said bus cycle including at least one clock cycle and involves bus access; determination means for determining at or about the start of said bus cycle if said bus cycle being controlled by the central processing unit means is a predetermined type of bus cycle and determining at or about the start of said bus cycle whether an address that is accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of the bus cycle type and address; maintaining means for maintaining said at least one identifying signal in a constant logic state for a predetermined period; frequency varying means for varying the frequency of the clock signal of the central processing unit based on the at least one identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit; whereby the running time of the central processing unit means varies based on the bus cycle type and address.
Claim 14
Independent Claim
163 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if an address accessed by the central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining said at least one identifying signal in a constant logic state for a predetermined period; varying a frequency of the clock signal of the central processing unit based on the identifying signal; and adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit; whereby the running time for processing data by the central processing unit is adjusted in accordance with the address accessed.
Claim 15
Independent Claim
163 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if an address accessed by the central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining said at least one identifying signal in a constant logic state for a predetermined period; varying a frequency of the clock signal of the central processing unit based on the identifying signal; and adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit; whereby the running time for processing data by the central processing unit is adjusted in accordance with the address accessed.
Claim 16
Dependent Claim
189 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle controlled by said central processing unit, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining means for maintaining said at least one identifying signal in a constant logic state for a predetermined period; frequency varying means for varying the frequency of the clock signal of the central processing unit means in accordance with the at least one identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit means; whereby the running time of the central processing unit means varies based on the address accessed.
Claim 17
Dependent Claim
189 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle controlled by said central processing unit, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining means for maintaining said at least one identifying signal in a constant logic state for a predetermined period; frequency varying means for varying the frequency of the clock signal of the central processing unit means in accordance with the at least one identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the varying of the frequency of the clock signal of the central processing unit means; whereby the running time of the central processing unit means varies based on the address accessed.
Claim 18
Dependent Claim
183 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle controlled by said central processing unit means, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit means is a predetermined type of bus cycle; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining means for maintaining said at least one identifying signal in a constant logic state for a predetermined period; extending means for extending at least one clock pulse period which, comprises said clock cycle based on the identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time of the central processing unit means varies based on the bus cycle type.
Claim 19
Dependent Claim
183 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle controlled by said central processing unit means, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit means is a predetermined type of bus cycle; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining means for maintaining said at least one identifying signal in a constant logic state for a predetermined period; extending means for extending at least one clock pulse period which, comprises said clock cycle based on the identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time of the central processing unit means varies based on the bus cycle type.
Claim 20
Independent Claim
162 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit is a predetermined type of bus cycle; producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining said at least one identifying signal in a constant logic state for a predetermined period; extending at least one clock pulse period which comprises said clock cycle based on the identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time for processing data by the central processing unit is adjusted based on the bus cycle type.
Claim 21
Independent Claim
162 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit is a predetermined type of bus cycle; producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining said at least one identifying signal in a constant logic state for a predetermined period; extending at least one clock pulse period which comprises said clock cycle based on the identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time for processing data by the central processing unit is adjusted based on the bus cycle type.
Claim 22
Dependent Claim
224 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle being controlled by said central processing unit, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit means is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of the bus cycle type and address; maintaining means for maintaining the at least one identifying signal in a constant logic level for a predetermined period; extending means for extending at least one clock pulse period which comprises said clock cycle based on the at least one identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time of the central processing unit means varies based on the bus cycle type and address.
Claim 23
Dependent Claim
224 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a bus cycle being controlled by said central processing unit, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit means is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of the bus cycle type and address; maintaining means for maintaining the at least one identifying signal in a constant logic level for a predetermined period; extending means for extending at least one clock pulse period which comprises said clock cycle based on the at least one identifying signal; and adjusting means for adjusting a timing of a control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time of the central processing unit means varies based on the bus cycle type and address.
Claim 24
Independent Claim
201 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by the central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of bus cycle type and address; maintaining the at least one identifying signal in a constant logic state for a predetermined period; extending at least one clock pulse period which comprises said clock cycle based on the at least one identifying signal; and adjusting the timing of the control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time for processing data by the central processing unit is adjusted based on the bus cycle type and address.
Claim 25
Independent Claim
201 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if the bus cycle controlled by said central processing unit is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by the central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of bus cycle type and address; maintaining the at least one identifying signal in a constant logic state for a predetermined period; extending at least one clock pulse period which comprises said clock cycle based on the at least one identifying signal; and adjusting the timing of the control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time for processing data by the central processing unit is adjusted based on the bus cycle type and address.
Claim 26
Independent Claim
154 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if an address accessed by the central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining the identifying signal in a constant logic state for a predetermined period; extending at least one clock pulse period which comprises said clock cycle based on the identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said at least one clock pulse; whereby the running time for processing data by the central processing unit is adjusted based on the address accessed.
Claim 27
Independent Claim
154 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if an address accessed by the central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining the identifying signal in a constant logic state for a predetermined period; extending at least one clock pulse period which comprises said clock cycle based on the identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said at least one clock pulse; whereby the running time for processing data by the central processing unit is adjusted based on the address accessed.
Claim 28
Dependent Claim
182 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a unit of a bus cycle being controlled by the central processing unit, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining means for maintaining the identifying signal in a constant logic state for a predetermined period; extending means for extending at least one clock pulse period which comprises said clock cycle based on the at least one identifying signal; and adjusting means for adjusting the timing of the control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time of the central processing unit means varies based on the address accessed.
Claim 29
Dependent Claim
182 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a unit of a bus cycle being controlled by the central processing unit, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining means for maintaining the identifying signal in a constant logic state for a predetermined period; extending means for extending at least one clock pulse period which comprises said clock cycle based on the at least one identifying signal; and adjusting means for adjusting the timing of the control signal which controls bus access at or about the extending of said at least one clock pulse period; whereby the running time of the central processing unit means varies based on the address accessed.
Claim 30
Independent Claim
173 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if said bus cycle controlled by the central processing unit is a predetermined type of bus cycle; producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining the at least one identifying signal in a constant logic state for a predetermined period; extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time for processing data by the central processing unit is adjusted based on the bus cycle type.
Claim 31
Independent Claim
173 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if said bus cycle controlled by the central processing unit is a predetermined type of bus cycle; producing at least one identifying signal indicating the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining the at least one identifying signal in a constant logic state for a predetermined period; extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time for processing data by the central processing unit is adjusted based on the bus cycle type.
Claim 32
Dependent Claim
20 words
The method as claimed in claim 16, including setting the value of said integer M based on a computer program.
Claim 33
Independent Claim
209 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if said bus cycle controlled by the central processing unit is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by the central processing predetermined address range; unit is in a producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of bus cycle type and address; maintaining the at least one identifying signal in a constant logic state for a predetermined period; extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time for processing data by the central processing unit is adjusted based on the bus cycle type and address.
Claim 34
Independent Claim
209 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if said bus cycle controlled by the central processing unit is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by the central processing predetermined address range; unit is in a producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of bus cycle type and address; maintaining the at least one identifying signal in a constant logic state for a predetermined period; extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time for processing data by the central processing unit is adjusted based on the bus cycle type and address.
Claim 35
Independent Claim
169 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if an address accessed by the central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining the identifying signal at a constant logic level for a predetermined period; extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the at least one identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time for processing data by the central processing unit is adjusted based on the address accessed.
Claim 36
Independent Claim
169 words
A method for controlling the running time of a central processing unit which operates in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access, comprising: determining, at or about the start of said bus cycle, if an address accessed by the central processing unit is in a predetermined address range; producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining the identifying signal at a constant logic level for a predetermined period; extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the at least one identifying signal; and adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time for processing data by the central processing unit is adjusted based on the address accessed.
Claim 37
Dependent Claim
196 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device based on a bus cycle controlled by said central processing unit means, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if said bus cycle controlled by said central processing unit means is a predetermined type of bus cycle; signal producing means for producing at least one identifying signal representing the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining means for maintaining the at least one identifying signal in a constant logic state for a predetermined period; extending means for extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the at least one identifying signal; and adjusting means for adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time of the central processing unit means varies based on the bus cycle type.
Claim 38
Dependent Claim
196 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device based on a bus cycle controlled by said central processing unit means, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if said bus cycle controlled by said central processing unit means is a predetermined type of bus cycle; signal producing means for producing at least one identifying signal representing the predetermined bus cycle in accordance with the determination of bus cycle type; maintaining means for maintaining the at least one identifying signal in a constant logic state for a predetermined period; extending means for extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the at least one identifying signal; and adjusting means for adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time of the central processing unit means varies based on the bus cycle type.
Claim 39
Dependent Claim
231 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if said bus cycle controlled by said central processing unit means is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of the bus cycle type and address; maintaining means for maintaining the at least one identifying signal at a constant logic level for a predetermined period; extending means for extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the at least one identifying signal; and adjusting means for adjusting the timing of the control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time of the central processing unit means varies based on the bus cycle type and address.
Claim 40
Dependent Claim
231 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if said bus cycle controlled by said central processing unit means is a predetermined type of bus cycle and determining, at or about the start of said bus cycle, whether an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined bus cycle and the predetermined address range access in accordance with the determination of the bus cycle type and address; maintaining means for maintaining the at least one identifying signal at a constant logic level for a predetermined period; extending means for extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the at least one identifying signal; and adjusting means for adjusting the timing of the control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time of the central processing unit means varies based on the bus cycle type and address.
Claim 41
Dependent Claim
186 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining means for maintaining the identifying signal at a constant logic level for a predetermined period; extending means for extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the at least one identifying signal; and adjusting means for adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time of the central processing unit means varies based on the address accessed.
Claim 42
Dependent Claim
186 words
A data processing apparatus, comprising: central processing unit means for accessing memory and at least one peripheral device in accordance with a unit of a bus cycle, said bus cycle including at least one clock cycle and involves bus access; determination means for determining, at or about the start of said bus cycle, if an address accessed by the central processing unit means is in a predetermined address range; signal producing means for producing at least one identifying signal indicating the predetermined address range access in accordance with the determination of address; maintaining means for maintaining the identifying signal at a constant logic level for a predetermined period; extending means for extending the period of M clock pulses of said clock cycle comprising N clock pulses (M being an integer, M≦N) based on the at least one identifying signal; and adjusting means for adjusting the timing of a control signal which controls bus access at or about the extending of said period of M clock pulses of said clock cycle; whereby the running time of the central processing unit means varies based on the address accessed.
Claim 43
Dependent Claim
37 words
The method as claimed in claim 3, wherein the frequency of the clock signal is increased when the line voltage is high and the frequency of the clock signal is decreased when the line voltage is low.
Claim 44
Dependent Claim
39 words
The data processing apparatus as claimed in claim 4, wherein the frequency of the clock signal is increased when the line voltage is high and the frequency of the clock signal is decreased when the line voltage is low.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |