Transistor circuit for holding peak/bottom level of signal

Claim 2

A transistor circuit comprising a first transistor supplied with an input voltage and connected between a first power supply line and an output terminal, a capacitor connected between said output terminal and a second power supply line and producing an output voltage at said output terminal, said first transistor, when rendered conductive, charging said capacitor with a first current, a second transistor supplied with said input voltage and producing a second current responsive to said input voltage irrespective of whether said input voltage is larger or smaller than said output voltage, and a current circuit coupled to receive said second current and discharging said capacitor with a third current relative to said second current, said third current for discharging said capacitor existing concurrently with and being smaller than said first current to thereby allow said output voltage to follow said input voltage when said first transistor is rendered conductive.

Claim 3

The transistor circuit as claimed in claim 1, wherein said current circuit comprises a current mirror circuit having an input node connected to said second transistor and an output node connected to said output terminal, and being responsive to said second current supplied to said input node to produce said third current at said output node.

Claim 4

The transistor circuit as claimed in claim 2, wherein said first and second transistors have the same threshold voltage as each other.

Claim 5

The transistor circuit as claimed in claim 2, wherein said first transistor has a first threshold voltage smaller than a second threshold voltage of said second transistor.

Claim 6

A transistor circuit comprising a first transistor connected between a first power supply line and an output terminal and having a gate supplied with an input voltage, a capacitor connected between said output terminal and a second power supply line and producing an output voltage at said output terminal, said first transistor being rendered conductive to charge said capacitor with a first current when said input voltage is larger in absolute value than said output voltage, a second transistor connected between said first power supply line and a circuit node and having a gate supplied with said input voltage, a third transistor connected between said circuit node and said second power supply line and having a gate connected to said circuit node, said second transistor being rendered conductive in response to said input voltage to produce a second current irrespective of said output voltage, and a fourth transistor connected between said output terminal and said second power supply line and having a gate connected to the gate of said third transistor, said fourth transistor cooperating with said third transistor to constitute a current mirror circuit to produce a third current that is relative to said second current and smaller than said first current, and discharging said capacitor with said third current.

Claim 7

A transistor circuit comprising a first transistor connected between a first power supply line and an output terminal and having a gate supplied with an input voltage, a capacitor connected between said output terminal and a second power supply line and producing an output voltage at said output terminal, said first transistor being rendered conductive to charge said capacitor with a first current when said input voltage is larger in absolute value than said output voltage, a second transistor connected between said first power supply line and a circuit node and having a gate supplied with said input voltage, a third transistor connected between said circuit node and said second power supply line and having a gate connected to said circuit node, said second transistor being rendered conductive in response to said input voltage to produce a second current irrespective of said output voltage, and a fourth transistor connected between said output terminal and said second power supply line and having a gate connected to the gate of said third transistor, said fourth transistor cooperating with said third transistor to constitute a current mirror circuit to produce a third current that is relative to said second current and smaller than said first current, and discharging said capacitor with said third current.

Claim 8

The transistor circuit as claimed in claim 5, wherein said first, second, third and fourth transistors have channel types equal to one another.

Claim 9

The transistor circuit as claimed in claim 6, said second transistor having a second threshold voltage larger than a first threshold voltage of said first transistor.

Claim 10

The transistor circuit as claimed in claim 6, said first transistor having a first threshold voltage substantially equal to a second threshold voltage of said second transistor.