US4987323A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peak voltage holding circuit
Assignee: NEC Corp
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Filing: 1989-07-27
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Granted: 1991-01-22
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Expires: 2009-07-27
Abstract
Abstract In a peak voltage holding circuit, a leakage circuit includes a first-stage mirror circuit, a second-stage mirror circuit, a selecting circuit, a capacitor, and a control circuit. The first-stage mirror circuit has one end connected to a second potential. The second-stage mirror circuit has one end connected to the output side of an input circuit and the other end connected to a first potential, and causes a current corresponding to a current which flows through the first-stage mirror circuit connected to the first potential to flow out from the voltage holding capacitor. The selecting circuit is connected the other end of the first-stage mirror circuit. The capacitor has one end connected to the selecting circuit and the other end connected to the first potential. The control circuit is connected to the selecting circuit and controls an operation of the selecting circuit. The selecting circuit alternately connects one end of the capacitor to the other end of the first-stage mirror circuit and the first potential at every arbitrary period.
Inventors
- 👤 Tsuneo Fujita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:51
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/04
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
A peak voltage holding circuit having: input means for inputting an analog voltage said input means having an output side; a voltage holding capacitor, having one end connected to an output side of said input means and an other end connected to a first potential, for holding a peak value of the analog voltage; leakage means, connected in parallel with said voltage holding capacitor, for gradually leaking the analog voltage held by said voltage holding capacitor; and output means, connected to the output side of said input means, for outputting the peak value of the analog voltage held by said voltage holding capacitor, wherein said leakage means comprises: a first-stage mirror circuit having one end connected to a second potential and having another end; a second-stage mirror circuit, having one end connected to the output side of said input means and another end connected to the first potential, for causing a current corresponding to a current which flows through said first-stage mirror circuit to flow out from said voltage holding capacitor; a selecting circuit connected to the other end of said first-stage mirror circuit; a capacitor having one end connected to said selecting circuit and another end connected to the first potential; and a control circuit, connected to said selecting circuit, for controlling an operation of said selecting circuit, said selecting circuit alternately connecting one end of said capacitor to the other end of said first-stage mirror circuit and the first potential at every arbitrary period.
Claim 2
Dependent Claim
246 words
A peak voltage holding circuit having: input means for inputting an analog voltage said input means having an output side; a voltage holding capacitor, having one end connected to an output side of said input means and an other end connected to a first potential, for holding a peak value of the analog voltage; leakage means, connected in parallel with said voltage holding capacitor, for gradually leaking the analog voltage held by said voltage holding capacitor; and output means, connected to the output side of said input means, for outputting the peak value of the analog voltage held by said voltage holding capacitor, wherein said leakage means comprises: a first-stage mirror circuit having one end connected to a second potential and having another end; a second-stage mirror circuit, having one end connected to the output side of said input means and another end connected to the first potential, for causing a current corresponding to a current which flows through said first-stage mirror circuit to flow out from said voltage holding capacitor; a selecting circuit connected to the other end of said first-stage mirror circuit; a capacitor having one end connected to said selecting circuit and another end connected to the first potential; and a control circuit, connected to said selecting circuit, for controlling an operation of said selecting circuit, said selecting circuit alternately connecting one end of said capacitor to the other end of said first-stage mirror circuit and the first potential at every arbitrary period.
Claim 3
Dependent Claim
76 words
A circuit according to claim 1, wherein said selecting circuit comprises first and second switches each having control, first and second electrodes, and the control electrodes of said first and second switches being connected to said control circuit, the first electrode of said first switch being connected to the other end of said first-stage mirror circuit, the second electrodes of said first and second switches being connected in common to said one end of said capacitor.
Claim 4
Dependent Claim
16 words
A circuit according to claim 1, wherein said first and second mirror circuits comprise CMOS transistors.
Claim 5
Dependent Claim
15 words
A circuit according to claim 2, wherein said first and second switches comprise CMOS transistors.
Claim 6
Dependent Claim
161 words
A peak voltage holding circuit comprising: means, having a first capacitor, for detecting a peak level of an input signal and for causing said first capacitor to hold a voltage corresponding to the peak level; first and second current mirror circuits each having a current input terminal and a current output terminal; means for connecting said current output terminal of said first current mirror circuit to said first capacitor; means for connected said current output terminal of said second current mirror circuit to said current input terminal of said first current mirror circuit; a second capacitor having one end connected to a reference voltage point and having another end; first switching means connected between said other end of said second capacitor and said current input terminal of said second current mirror circuit; second switching means connected between said other end of said second capacitor and said reference voltage point; and control means for alternately operating said first and second switching means.
Claim 7
Dependent Claim
161 words
A peak voltage holding circuit comprising: means, having a first capacitor, for detecting a peak level of an input signal and for causing said first capacitor to hold a voltage corresponding to the peak level; first and second current mirror circuits each having a current input terminal and a current output terminal; means for connecting said current output terminal of said first current mirror circuit to said first capacitor; means for connected said current output terminal of said second current mirror circuit to said current input terminal of said first current mirror circuit; a second capacitor having one end connected to a reference voltage point and having another end; first switching means connected between said other end of said second capacitor and said current input terminal of said second current mirror circuit; second switching means connected between said other end of said second capacitor and said reference voltage point; and control means for alternately operating said first and second switching means.
References Cited (Backward Citations)
US4400633A
Cited
JPS59216063A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |