US3694748A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peak-to-peak detector
Assignee: Hekimian Laboratories Inc
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Filing: 1971-07-19
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Granted: 1972-09-26
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Expires: 1991-07-19
Abstract
Abstract A peak-to-peak detector includes an operational amplifier driving the bases of two complementary transistor switches in parallel, amplifier feedback being provided from the collectors of the transistors. Each transistor conducts in response to a different input signal polarity and, when conducting, permits a capacitor in its emitter circuit to charge to the peak amplifier output voltage. The charged capacitors bias their respective transistors off until the amplifier output voltage exceeds the stored capacitor voltage. The sum of the stored capacitor voltages is a measure of the peak-to-peak input voltage.
Inventors
- 👤 Norris C Hekimian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:40
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/04
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
260 words
A peak-to-peak detector, comprising: an operational amplifier having an input terminal adapted to receive a polarity-varying input signal and an output terminal providing an amplified version of said input signal; an NPN transistor having base emitter and collector electrodes; a PNP transistor having base, emitter and collector electrodes; means connecting said output terminal to the base electrodes of both of said transistors; a feedback resistor connected between said input terminal and the collector electrodes of both of said transistors; a first storage capacitor connected between the emitter electrode of said NPN transistor and ground; and a second storage capacitor connected between the emitter electrode of said PNP transistor and ground; wherein said NPN transistor is rendered conductive by a signal of one polarity at said output terminal to permit said first storage capacitor to charge to the peak voltage across said feedback resistor, the resulting charge across said first storage capacitor biasing said NPN transistor off unless a voltage of said one polarity in excess of said resulting charge is developed at said output terminal to permit further charging of said first capacitor; and wherein said PNP transistor is rendered conductive by a signal of polarity opposite said one polarity at said output terminal to permit said second storage capacitor to charge to the peak voltage across said feedback resistor, the resulting charge across said second storage capacitor biasing said PNP transistor off unless a voltage of said opposite polarity in excess of said resulting charge is developed at said output terminal to permit further charging of said second capacitor.
Claim 2
Dependent Claim
260 words
A peak-to-peak detector, comprising: an operational amplifier having an input terminal adapted to receive a polarity-varying input signal and an output terminal providing an amplified version of said input signal; an NPN transistor having base emitter and collector electrodes; a PNP transistor having base, emitter and collector electrodes; means connecting said output terminal to the base electrodes of both of said transistors; a feedback resistor connected between said input terminal and the collector electrodes of both of said transistors; a first storage capacitor connected between the emitter electrode of said NPN transistor and ground; and a second storage capacitor connected between the emitter electrode of said PNP transistor and ground; wherein said NPN transistor is rendered conductive by a signal of one polarity at said output terminal to permit said first storage capacitor to charge to the peak voltage across said feedback resistor, the resulting charge across said first storage capacitor biasing said NPN transistor off unless a voltage of said one polarity in excess of said resulting charge is developed at said output terminal to permit further charging of said first capacitor; and wherein said PNP transistor is rendered conductive by a signal of polarity opposite said one polarity at said output terminal to permit said second storage capacitor to charge to the peak voltage across said feedback resistor, the resulting charge across said second storage capacitor biasing said PNP transistor off unless a voltage of said opposite polarity in excess of said resulting charge is developed at said output terminal to permit further charging of said second capacitor.
Claim 3
Dependent Claim
48 words
The circuit according to claim 1 further comprising a first relatively high resistance connected in parallel with said first storage capacitor and a second relatively large resistance connected in parallel with said second storage capacitor, said first and second high resistances permitting relatively slow discharge of said capacitors.
Claim 4
Dependent Claim
28 words
The circuit according to claim 1 further comprising metering means connected between said emitter electrodes to measure the sum of the voltages across said first and second capacitors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-26 | 1976-03-27 | 1976-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-26 | 1980-03-27 | 1980-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-26 | 1984-03-27 | 1984-09-26 | $7700.00 | Window Closed / Lapsed |