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US5469085A
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Source follower using two pairs of NMOS and PMOS transistors
Assignee: Individual
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Filing: 1992-01-13
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Granted: 1995-11-21
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Expires: 2012-01-13
Abstract
Abstract PCT No. PCT/JP92/00019 Sec. 371 Date Oct. 13, 1993 Sec. 102(e) Date Oct. 13, 1993 PCT Filed Jan. 13, 1992 PCT Pub. No. WO92/12575 PCT Pub. Date Jul. 23, 1992.A source follower circuit which operates at high speed and maintains low power consumption and which includes a pair of small, normally on, NMOS and PMOS transistors and a pair of large, normally off, NMOS and PMOS transistors. The two pairs of transistors are connected in parallel. In each pair of transistors the sources and the gates of the NMOS and PMOS transistors are connected to each other. Furthermore, the threshold voltages of the transistors must be set so that: large NMOS transistor voltage>small PMOS transistor voltage>small NMOS transistor voltage>large PMOS transistor voltage, or so that small PMOS transistor voltage>large NMOS transistor voltage>large PMOS transistor voltage>small NMOS transistor voltage.
Inventors
- 👤 Tadashi Shibata
- 👤 Tadahiro Ohmi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:09
CPC Classifications
G; G06; G06N; G06N3/00; G06N3/02; G06N3/06; G06N3/063; G06N3/065; H; H03; H03F; H03F3/00; H03F3/50; H03F3/505; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K17/164; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
206 words
A source follower circuit comprising: a first NMOS transistor having a first source, a first drain, and a first floating gate; a second NMOS transistor having a second source, a second drain, and a second floating gate; a first PMOS transistor having a third source, a third drain, and a third floating gate; a second PMOS transistor having a fourth source, a fourth drain, and a fourth floating gate; said first, second, third, and fourth sources connected together and to an output terminal; said first and second drains connected together; said third and fourth drains connected together; said first, second, third, and fourth floating gates connected together; and a plurality of input gates respectively connected to a plurality of input terminals and capacitively coupled to one or more of said floating gates; the threshold voltages of said first, second, third, and fourth transistors selected so that they comply with one of V.sub.TN2 >V.sub.TP1 >V.sub.TN1 >V.sub.TP2 and V.sub.TP1 >V.sub.TN2 >V.sub.TP2 >V.sub.TN1 wherein V TN1 is a threshold voltage of said first NMOS transistor; V TN2 is the threshold voltage of said second NMOS transistor; V TP1 is a threshold voltage of said first PMOS transistor; and V TP2 is the threshold voltage of said second PMOS transistor.
Claim 2
Dependent Claim
206 words
A source follower circuit comprising: a first NMOS transistor having a first source, a first drain, and a first floating gate; a second NMOS transistor having a second source, a second drain, and a second floating gate; a first PMOS transistor having a third source, a third drain, and a third floating gate; a second PMOS transistor having a fourth source, a fourth drain, and a fourth floating gate; said first, second, third, and fourth sources connected together and to an output terminal; said first and second drains connected together; said third and fourth drains connected together; said first, second, third, and fourth floating gates connected together; and a plurality of input gates respectively connected to a plurality of input terminals and capacitively coupled to one or more of said floating gates; the threshold voltages of said first, second, third, and fourth transistors selected so that they comply with one of V.sub.TN2 >V.sub.TP1 >V.sub.TN1 >V.sub.TP2 and V.sub.TP1 >V.sub.TN2 >V.sub.TP2 >V.sub.TN1 wherein V TN1 is a threshold voltage of said first NMOS transistor; V TN2 is the threshold voltage of said second NMOS transistor; V TP1 is a threshold voltage of said first PMOS transistor; and V TP2 is the threshold voltage of said second PMOS transistor.
Claim 3
Dependent Claim
182 words
A source follower circuit comprising: a first NMOS transistor having a first source, a first drain, and a first gate; a second NMOS transistor having a second source, a second drain, and a second gate; a first PMOS transistor having a third source, a third drain, and a third gate; a second PMOS transistor having a fourth source, a fourth drain, and a fourth gate; said first, second, third, and fourth sources connected together and to an output terminal; said first and second drains connected together; said third and fourth drains connected together; said first, second, third, and fourth gates connected together and to an input terminal; and the threshold voltages of said first, second, third, and fourth transistors selected so that they comply with one of V.sub.TN2 >V.sub.TP1 >V.sub.TN1 >V.sub.TP2 and V.sub.TP1 >V.sub.TN2 >V.sub.TP2 >V.sub.TN1 wherein V TN1 is a threshold voltage of said first NMOS transistor; V TN2 is the threshold voltage of said second NMOS transistor; V TP1 is a threshold voltage of said first PMOS transistor; and V TP2 is the threshold voltage of said second PMOS transistor.
Claim 4
Dependent Claim
182 words
A source follower circuit comprising: a first NMOS transistor having a first source, a first drain, and a first gate; a second NMOS transistor having a second source, a second drain, and a second gate; a first PMOS transistor having a third source, a third drain, and a third gate; a second PMOS transistor having a fourth source, a fourth drain, and a fourth gate; said first, second, third, and fourth sources connected together and to an output terminal; said first and second drains connected together; said third and fourth drains connected together; said first, second, third, and fourth gates connected together and to an input terminal; and the threshold voltages of said first, second, third, and fourth transistors selected so that they comply with one of V.sub.TN2 >V.sub.TP1 >V.sub.TN1 >V.sub.TP2 and V.sub.TP1 >V.sub.TN2 >V.sub.TP2 >V.sub.TN1 wherein V TN1 is a threshold voltage of said first NMOS transistor; V TN2 is the threshold voltage of said second NMOS transistor; V TP1 is a threshold voltage of said first PMOS transistor; and V TP2 is the threshold voltage of said second PMOS transistor.
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