US5465341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Verifiable security circuitry for preventing unauthorized access to programmed read only memory
Assignee: NXP BV
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Filing: 1992-10-23
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Granted: 1995-11-07
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Expires: 2012-10-23
Abstract
Abstract A security system is used for programmable read-only memory locations within a very large scale integrated (VLSI) circuit. In a first security bit memory location there is stored a first security data bit. The first security data bit has a first value when the first security bit memory location is unprogrammed and a second value when the first security bit memory location is programmed. In a second security bit memory location there is stored a second security data bit. The second security data bit has the first value when the second security bit memory location is unprogrammed and the second value when the second security bit memory location is programmed. A selection logic is electrically coupled to the first security bit memory location and the second security bit memory location. The selection logic selects no security data bit, the first security data bit or the second security data bit to be used to generate a security access signal. An access logic allows and prevents direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal. The access logic prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection logic selects no security data bit, when the selection logic selects the first security bit and the first security data bit has the second value, or when the selection logic selects the second security bit and the second security data bit has the second value.
Inventors
- 👤 Bryan C. Doi
- 👤 Steven D. Thomas
- 👤 Vincent J. Coli
- 👤 Vito D. Giglio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:27
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/24; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433; G11C16/00; G11C16/02; G11C16/06; G11C16/22
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
289 words
A security system for programmable read-only memory locations within a very large scale integrated (VLSI) circuit, the security system comprising: a first security bit memory location in which is stored a first security data bit, the first security data bit having a first value when the first security bit memory location is unprogrammed and the first security data bit having a second value when the first security bit memory location is programmed; a second security bit memory location in which is stored a second security data bit, the second security data bit having the first value when the second security bit memory location is unprogrammed and the second security data bit having the second value when the second security bit memory location is programmed; selection means, electrically coupled to the first security bit memory location and the second security bit memory location, for selecting to provide a value for a security access signal, one of the first security data bit, the second security data bit or neither the first security data bit nor the second security data bit; and, access means, coupled to the selection means, for allowing and preventing direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal; wherein the access means prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection means selects neither the first security data bit nor the second security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
Claim 2
Dependent Claim
289 words
A security system for programmable read-only memory locations within a very large scale integrated (VLSI) circuit, the security system comprising: a first security bit memory location in which is stored a first security data bit, the first security data bit having a first value when the first security bit memory location is unprogrammed and the first security data bit having a second value when the first security bit memory location is programmed; a second security bit memory location in which is stored a second security data bit, the second security data bit having the first value when the second security bit memory location is unprogrammed and the second security data bit having the second value when the second security bit memory location is programmed; selection means, electrically coupled to the first security bit memory location and the second security bit memory location, for selecting to provide a value for a security access signal, one of the first security data bit, the second security data bit or neither the first security data bit nor the second security data bit; and, access means, coupled to the selection means, for allowing and preventing direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal; wherein the access means prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection means selects neither the first security data bit nor the second security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
Claim 3
Dependent Claim
159 words
A security system as in claim 1 wherein the VLSI circuit includes input pins, output pins and additional logic circuitry, the additional logic circuitry having address lines and data lines and the additional logic circuit controlling operation of the VLSI circuit; and, wherein the access means includes a first multiplexor, coupled to the input pins and the address lines of the additional circuitry, the first multiplexor selecting between an address on the address lines of the additional logic circuitry and information on the input pins of the VLSI circuit to be connected to input address lines for the programmable read only memory locations, and a second multiplexor, coupled to the output pins, the programmable read-only memory locations and the data lines for the additional logic circuitry, the second multiplexor selecting between the data lines for the additional logic circuitry and data from the programmable read only memory locations to be placed on the output pins of the VLSI circuit.
Claim 4
Dependent Claim
57 words
A security system as in claim 2 wherein the additional logic circuitry generates a test bit and wherein the access means includes means, coupled to the additional logic circuitry, for preventing any device outside the VLSI circuit from having direct access to the programmable read-only memory locations when the test bit has a first test bit value.
Claim 5
Dependent Claim
73 words
A security system as in claim 1 wherein the programmable read-only memory locations are arranged in a memory array within a programmable read-only memory (PROM), the PROM additionally including an address decoder, coupled to the programmable read-only memory locations, and wherein the programmable read-only memory locations include programmable read only memory locations which form a test row, a test column, the first security bit memory location and the second security bit memory location.
Claim 6
Dependent Claim
114 words
A security system as in claim 1 wherein the VLSI circuit additionally includes program logic, coupled to the programmable read-only memory locations, for providing a programming voltage to the programmable read-only memory locations, the program logic including enable/disable means, coupled to the selection means, for preventing the program logic from programming the programmable read-only memory locations when the selection means selects neither the first security data bit nor the second security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
Claim 7
Independent Claim
137 words
A method for providing security for programmable read-only memory locations within a VLSI circuit, the VLSI circuit including a first security bit and a second security bit, wherein providing security for programmable read-only memory locations includes verification of correct operation of security features, the method comprising the steps of: (a) preventing, by the VLSI circuit, a device outside the VLSI circuit from accessing the programmable read-only memory locations except when the first security bit is selected and unprogrammed or when the second security bit is selected and unprogrammed; (b) programming test memory locations within the VLSI circuit; (c) programming the first security bit to a first value; (d) selecting the first security bit; and (e) while the first security bit is selected, verifying that no device outside the VLSI circuit can access the programmable read-only memory locations.
Claim 8
Independent Claim
137 words
A method for providing security for programmable read-only memory locations within a VLSI circuit, the VLSI circuit including a first security bit and a second security bit, wherein providing security for programmable read-only memory locations includes verification of correct operation of security features, the method comprising the steps of: (a) preventing, by the VLSI circuit, a device outside the VLSI circuit from accessing the programmable read-only memory locations except when the first security bit is selected and unprogrammed or when the second security bit is selected and unprogrammed; (b) programming test memory locations within the VLSI circuit; (c) programming the first security bit to a first value; (d) selecting the first security bit; and (e) while the first security bit is selected, verifying that no device outside the VLSI circuit can access the programmable read-only memory locations.
Claim 9
Dependent Claim
35 words
A method as in claim 6 additionally comprising the steps of: (f) selecting the second security bit; (g) programming the programmable read-only memory locations; and, (h) programming the second security bit to the first value.
Claim 10
Independent Claim
215 words
A method for providing security for programmable read-only memory locations within a VLSI circuit, the method comprising the steps of: (a) providing within the VLSI circuit a first security bit memory location in which is stored a first security data bit, the first security data bit having a first value when the first security bit memory location is unprogrammed and the first security data bit having a second value when the first security bit memory location is programmed; (b) providing within the VLSI circuit a second security bit memory location in which is stored a second security data bit, the second security data bit having the first value when the second security bit memory location is unprogrammed and the second security data bit having the second value when the second security bit memory location is programmed; and, (c) preventing, by the VLSI circuit, any device outside the VLSI circuit from directly accessing the programmable read-only memory locations when a selection means selects neither the first security data bit nor the second security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
Claim 11
Independent Claim
215 words
A method for providing security for programmable read-only memory locations within a VLSI circuit, the method comprising the steps of: (a) providing within the VLSI circuit a first security bit memory location in which is stored a first security data bit, the first security data bit having a first value when the first security bit memory location is unprogrammed and the first security data bit having a second value when the first security bit memory location is programmed; (b) providing within the VLSI circuit a second security bit memory location in which is stored a second security data bit, the second security data bit having the first value when the second security bit memory location is unprogrammed and the second security data bit having the second value when the second security bit memory location is programmed; and, (c) preventing, by the VLSI circuit, any device outside the VLSI circuit from directly accessing the programmable read-only memory locations when a selection means selects neither the first security data bit nor the second security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
Claim 12
Dependent Claim
45 words
A method as in claim 8 additionally comprising the step of: (d) preventing, by the VLSI circuit, any device outside the VLSI circuit from directly accessing the programmable read-only memory locations when a test bit, within the VLSI circuit, has a first test bit value.
Claim 13
Dependent Claim
75 words
A method as in claim 8 additionally comprising the step of: (d) preventing a programming voltage from being provided to the programmable read-only memory locations when the selection means selects no security data bit, when the selection means selects the first security data bit and the first security data bit has the second value, or when the selection means selects the second security data bit and the second security data bit has the second value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-06 | 1999-05-08 | 1999-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-06 | 2003-05-08 | 2003-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-06 | 2007-05-08 | 2007-11-07 | $7700.00 | Window Closed / Lapsed |