US5463240A
Expired / Lapsed
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CMIS device with increased gain
Assignee: NEC Electronics Corp
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Filing: 1994-11-01
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Granted: 1995-10-31
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Expires: 2014-11-01
Abstract
Abstract In a CMIS device having a semiconductor substrate including a first N-type region and a P-type region, a second P-type region is formed within the first N-type region, and a second N-type region is formed within the first P-type region. Also, a third N-type region is formed within the second P-type region, and a third N-type region is formed within the second N-type region. An N-channel transistor is formed by the first N-type region as a drain, the second P-type region as a channel, and the third N-type region as a source. A P-channel transistor is formed by the first P-type region as a drain, the second N-type region as a channel, and the third P-type region as a source.
Inventors
- 👤 Toshio Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:11
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/0175; H03K19/0185; H03K19/018557; H03K19/018571; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/857; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
207 words
A CMIS device comprising: a semiconductor substrate including a first N-type region for a drain of an N-channel transistor and a first P-type region for a drain of a P-channel transistor; a second P-type region formed within said first N-type region, a surface of said second P-type region being for a channel of said N-channel transistor; a second N-type region formed within said first P-type region, a surface of said second N-type region being for a channel of said P-channel transistor; a third N-type region formed within said second P-type region, said third N-type region being for a source of said N-channel transistor; a third P-type region formed within said second N-type region, said third P-type region being for a source of said P-channel transistor; a first gate electrode formed above said second P-type region; a second gate electrode formed above said second N-type region; said first N-type region being connected to a first power supply means for receiving a first voltage; said first P-type region being connected to a second power supply means for receiving a second voltage lower than the first voltage; means for connecting said second P-type region, said second N-type region, said third N-type region and said third P-type region to each other.
Claim 2
Dependent Claim
207 words
A CMIS device comprising: a semiconductor substrate including a first N-type region for a drain of an N-channel transistor and a first P-type region for a drain of a P-channel transistor; a second P-type region formed within said first N-type region, a surface of said second P-type region being for a channel of said N-channel transistor; a second N-type region formed within said first P-type region, a surface of said second N-type region being for a channel of said P-channel transistor; a third N-type region formed within said second P-type region, said third N-type region being for a source of said N-channel transistor; a third P-type region formed within said second N-type region, said third P-type region being for a source of said P-channel transistor; a first gate electrode formed above said second P-type region; a second gate electrode formed above said second N-type region; said first N-type region being connected to a first power supply means for receiving a first voltage; said first P-type region being connected to a second power supply means for receiving a second voltage lower than the first voltage; means for connecting said second P-type region, said second N-type region, said third N-type region and said third P-type region to each other.
Claim 3
Dependent Claim
83 words
A device as set forth in claim 1, wherein said second P-type region is of a ring shape surrounding said third N-type region, said first N-type region being of a ring shape surrounding said second P-type region, said first gate electrode being of a ring shape, said second N-type region is of a ring shape surrounding said third P-type region, said first P-type region being of a ring shape surrounding said second N-type region, said second gate electrode being of a ring shape.
Claim 4
Dependent Claim
71 words
A device as set forth in claim 1, further comprising: a P-type contact region formed within said third N-type region and connected to said second P-type region; and an N-type contact region formed within said third P-type region and connected to said second P-type region, said connecting means being connected via said P-type contact region to said second P-type region and via said N-type contact region to said second N-type region.
Claim 5
Dependent Claim
69 words
A device as set forth in claim 3, further comprising an insulating layer formed on said semiconductor substrate, said insulating layer having a first contact hole commonly for said third N-type region and said P-type contact region and a second contact hole commonly for said third P-type region and said N-type contact region, said connecting means comprising a metal connection layer formed within said first and second contact holes.
Claim 6
Dependent Claim
20 words
A device as set forth in claim 3, wherein said P-type contact region and said N-type contact region are cylindrical.
Claim 7
Dependent Claim
30 words
A device as set forth in claim 1, further comprising: an input node connected to said first and second gate electrodes; and an output node connected to said connecting means.
Claim 8
Dependent Claim
25 words
A device as set forth in claim 1, wherein said first N-type region and said first P-type region are of an offset type drain structure.
Claim 9
Dependent Claim
116 words
A CMIS device comprising: a first power supply means for receiving a first voltage; a second power supply means for receiving a second voltage lower than the first voltage; an input node; an output node; an N-channel enhancement-type transistor having a drain region connected to said first power supply means, a source region connected to said output node, a channel region connected to said output node, and a gate electrode connected to said input node; and a P-channel enhancement-type transistor having a drain region connected to said second power supply means, a source region connected to said output node, a channel region connected to said output node, and a gate electrode connected to said input node.
Claim 10
Dependent Claim
116 words
A CMIS device comprising: a first power supply means for receiving a first voltage; a second power supply means for receiving a second voltage lower than the first voltage; an input node; an output node; an N-channel enhancement-type transistor having a drain region connected to said first power supply means, a source region connected to said output node, a channel region connected to said output node, and a gate electrode connected to said input node; and a P-channel enhancement-type transistor having a drain region connected to said second power supply means, a source region connected to said output node, a channel region connected to said output node, and a gate electrode connected to said input node.
Claim 11
Dependent Claim
77 words
A device as set forth in claim 8, further comprising: a first level shifter circuit, connected between said input node and the gate electrode of said N-type enhancement-type transistor, for shifting up a voltage at said input node by a first definite value; and a second level shifter circuit, connected between said input node and the gate electrode of said N-type enhancement-type transistor, for shifting down the voltage at said input node by a second definite value.
Claim 12
Dependent Claim
55 words
A device as set forth in claim 9, wherein said first level shifter comprises: a first load element connected to said first power supply means; and a P-channel source follower, connected between said first load element and said second power supply means, for shifting up the voltage at said input node by the first value.
Claim 13
Dependent Claim
55 words
A device as set forth in claim 9, wherein said second level shifter comprises: a second load element connected to said second power supply means; and an N-channel source follower, connected between said second load element and said first power supply means, for shifting down the voltage at said input node by the second value.
Claim 14
Dependent Claim
146 words
A CMIS device comprising: a semiconductor substrate including a first N-type region for a drain of an N-channel transistor and a first P-type region for a drain of a P-channel transistor; a second P-type region formed within said first N-type region, a surface of said second P-type region being for a channel of said N-channel transistor; a second N-type region formed within said first P-type region, a surface of said second N-type region being for a channel of said P-channel transistor; a third N-type region formed within said second P-type region, said third N-type region being for a source of said N-channel transistor; a third P-type region formed within said second N-type region, said third P-type region being for a source of said P-channel transistor; a first gate electrode formed above said second P-type region; and a second gate electrode formed above said second N-type region.
Claim 15
Dependent Claim
146 words
A CMIS device comprising: a semiconductor substrate including a first N-type region for a drain of an N-channel transistor and a first P-type region for a drain of a P-channel transistor; a second P-type region formed within said first N-type region, a surface of said second P-type region being for a channel of said N-channel transistor; a second N-type region formed within said first P-type region, a surface of said second N-type region being for a channel of said P-channel transistor; a third N-type region formed within said second P-type region, said third N-type region being for a source of said N-channel transistor; a third P-type region formed within said second N-type region, said third P-type region being for a source of said P-channel transistor; a first gate electrode formed above said second P-type region; and a second gate electrode formed above said second N-type region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-30 | 1999-05-01 | 1999-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-30 | 2003-05-01 | 2003-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-30 | 2007-05-01 | 2007-10-31 | $7700.00 | Window Closed / Lapsed |