Patent US5829879A successfully refreshed from Google Patents.
Patent US5462889A successfully refreshed from Google Patents.
US5462889A
Expired / Lapsed
US
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Method of fabricating a semiconductor device with a polycrystalline silicon resistive layer
Assignee: Renesas Electronics Corp
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Filing: 1994-06-02
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Granted: 1995-10-31
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Expires: 2014-06-02
Abstract
Abstract Provided is a novel method of fabricating a polycrystalline silicon layer serving as a resistive element involved in a high frequency semiconductor integrated circuit device. The novel method essentially comprises following steps. A polycrystalline silicon layer is deposited on an insulation layer covering a semiconductor substrate, followed by a selective photo etching by using a photo resist as a mask, and further followed by a selective doping by using ion-implantation with employing a photo resist pattern so as to introduce dopant into the remaining polycrystalline silicon layer except for a peripheral area having a predetermined width thereby resulting in a resistive layer which comprises not only a doped area but an undped area fencing the doped area.
Inventors
- 👤 Michiko Tsukada
- 👤 Akio Matsuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:11
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
135 words
A method of fabricating a polycrystalline silicon layer serving as a resistive element involved in a semiconductor integrated circuit device, said method comprising the steps of: depositing a polycrystalline silicon layer on an insulation layer covering a semiconductor substrate; subjecting said deposited polycrystalline silicon layer to selective doping by using ion-implantation with employing a photo resist pattern; and subjecting said doped polycrystalline silicon layer to a selective etching by using a photo resist pattern as a mask so as to have said polycrystalline silicon layer remain at not only said doped area but an undoped peripheral area having a width of 0.5 to 1.5 micrometers, wherein said peripheral area acts as a buffer preventing variation of area, caused by variations in said selective etching, from occurring in a central portion of said polycrystalline silicon layer.
Claim 2
Independent Claim
135 words
A method of fabricating a polycrystalline silicon layer serving as a resistive element involved in a semiconductor integrated circuit device, said method comprising the steps of: depositing a polycrystalline silicon layer on an insulation layer covering a semiconductor substrate; subjecting said deposited polycrystalline silicon layer to selective doping by using ion-implantation with employing a photo resist pattern; and subjecting said doped polycrystalline silicon layer to a selective etching by using a photo resist pattern as a mask so as to have said polycrystalline silicon layer remain at not only said doped area but an undoped peripheral area having a width of 0.5 to 1.5 micrometers, wherein said peripheral area acts as a buffer preventing variation of area, caused by variations in said selective etching, from occurring in a central portion of said polycrystalline silicon layer.
Claim 3
Dependent Claim
45 words
The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 1, wherein said etching is accomplished by using a photo resist which covers not only said doped area but an undoped peripheral area of said polycrystalline silicon layer.
Claim 4
Dependent Claim
50 words
The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 1, further comprising the steps of: forming an insulation film so as to cover said doped polycrystalline silicon layer; and subjecting said covered polycrystalline silicon layer to a heat treatment for dopant activation.
Claim 5
Dependent Claim
51 words
The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 1, wherein said ion-implantation is accomplished with employing both a photo resist and a conductive metal layer underlying said photo resist, said conductive metal layer serving as a prevention against a charge-up of ions.
Claim 6
Dependent Claim
51 words
The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 1, wherein said ion-implantation is accomplished with employing both a photo resist and an insulation film underlying said photo resist, said insulation film serving as a prevention against a charge-up of high energy ions.
Claim 7
Independent Claim
204 words
A method of fabricating a high frequency semiconductor integrated circuit device including a polycrystalline silicon layer serving as a resistive element, said method comprising the steps of: forming an active region including at least one active element on a semiconductor substrate; forming an insulation layer so as to accomplish the isolation of said active element; forming an insulation film on an entire surface of said device so as to cover both said active region and said insulation layer; depositing a polycrystalline silicon layer on said insulation film; subjecting said deposited polycrystalline silicon layer to selective doping by using ion-implantation with employing a photo resist pattern as a mask so that dopant is introduced into a predetermined area over said insulation layer opposite to said active region; and subjecting said doped polycrystalline silicon layer to a selective etching by using a photo resist pattern as a mask so as to have said polycrystalline silicon layer remain at not only said doped area but an undoped peripheral area having a width of 0.5 to 1.5 micrometers, wherein said peripheral area acts as a buffer preventing variation of area, caused by variations in said selective etching, from occurring in a central portion of said polycrystalline silicon layer.
Claim 8
Independent Claim
204 words
A method of fabricating a high frequency semiconductor integrated circuit device including a polycrystalline silicon layer serving as a resistive element, said method comprising the steps of: forming an active region including at least one active element on a semiconductor substrate; forming an insulation layer so as to accomplish the isolation of said active element; forming an insulation film on an entire surface of said device so as to cover both said active region and said insulation layer; depositing a polycrystalline silicon layer on said insulation film; subjecting said deposited polycrystalline silicon layer to selective doping by using ion-implantation with employing a photo resist pattern as a mask so that dopant is introduced into a predetermined area over said insulation layer opposite to said active region; and subjecting said doped polycrystalline silicon layer to a selective etching by using a photo resist pattern as a mask so as to have said polycrystalline silicon layer remain at not only said doped area but an undoped peripheral area having a width of 0.5 to 1.5 micrometers, wherein said peripheral area acts as a buffer preventing variation of area, caused by variations in said selective etching, from occurring in a central portion of said polycrystalline silicon layer.
Claim 9
Dependent Claim
41 words
The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 6, wherein said ion-implantation is accomplished with employing a photo resist which covers only said undoped peripheral area of said remaining polycrystalline silicon layer.
Claim 10
Dependent Claim
50 words
The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 6, further comprising the steps of: forming an insulation film so as to cover said doped polycrystalline silicon layer; and subjecting said covered polycrystalline silicon layer to a heat treatment for dopant activation.
Claim 11
Dependent Claim
41 words
The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 8, wherein said heat treatment is accomplished so as to cause not only said dopant activation but a thermal diffusion for forming active elements.
Claim 12
Dependent Claim
45 words
The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 6, further comprising the steps of: forming contact electrodes of said active element, which comprises polycrystalline silicon after forming said polycrystalline silicon layer serving as a resistive element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-30 | 1999-05-01 | 1999-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-30 | 2003-05-01 | 2003-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-30 | 2007-05-01 | 2007-10-31 | $7700.00 | Window Closed / Lapsed |