Patent JPS5887746A successfully refreshed from Google Patents.
Patent US5460983A successfully refreshed from Google Patents.
US5460983A
Expired / Lapsed
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Method for forming isolated intra-polycrystalline silicon structures
Assignee: STMicroelectronics lnc USA
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Filing: 1993-07-30
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Granted: 1995-10-24
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Expires: 2013-07-30
Abstract
Abstract Therefore, according to the present invention, the isolation between adjacent intra-polycrystalline silicon layer components of one or more polycrystalline silicon layers of an integrated circuit device may be enhanced by patterning and then implanting one or more such polycrystalline silicon layers with a high dose of oxygen or nitrogen, in the range of approximately 1×10 17 /cm 2 to 1×10 19 /cm 2 . A post implant anneal is performed in either nitrogen or argon to form a layer of either silicon dioxide or silicon nitride having desirable planar characteristics. The anneal is performed at a temperature range of approximately 1000 to 1400 degrees Celsius.
Inventors
- 👤 Robert L. Hodges
- 👤 Frank R. Bryant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:04
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/40; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6725; H10D86/60; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/065; H10W20/0698
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
205 words
A method of forming a portion of a multiple layer integrated circuit device, comprising the steps of: forming first and second field effect transistors in a substrate, each field effect transistor having a gate formed from a first patterned layer of polycrystalline silicon and source/drain regions formed in the substrate; forming a first oxide layer over the field effect transistors and the substrate; forming an opening through the first oxide layer in a contact region, wherein a source/drain region of the first field effect transistor is exposed in the opening; forming a second layer of patterned polycrystalline silicon over the first oxide layer and in the opening to make contact with the exposed source/drain region; forming a layer of gate oxide over the second polycrystalline silicon layer and the first oxide layer; forming a third layer of polycrystalline silicon over the gate oxide layer; implanting oxygen into selected portions of the third polycrystalline silicon layer; annealing the device to convert the implanted oxygen in the selected portions into oxide, wherein portions of the third polycrystalline silicon layer not converted to oxide to define patterned interconnect; implanting impurities into the third polycrystalline silicon layer to form source/drain and channel regions in the third layer patterned interconnect.
Claim 2
Independent Claim
205 words
A method of forming a portion of a multiple layer integrated circuit device, comprising the steps of: forming first and second field effect transistors in a substrate, each field effect transistor having a gate formed from a first patterned layer of polycrystalline silicon and source/drain regions formed in the substrate; forming a first oxide layer over the field effect transistors and the substrate; forming an opening through the first oxide layer in a contact region, wherein a source/drain region of the first field effect transistor is exposed in the opening; forming a second layer of patterned polycrystalline silicon over the first oxide layer and in the opening to make contact with the exposed source/drain region; forming a layer of gate oxide over the second polycrystalline silicon layer and the first oxide layer; forming a third layer of polycrystalline silicon over the gate oxide layer; implanting oxygen into selected portions of the third polycrystalline silicon layer; annealing the device to convert the implanted oxygen in the selected portions into oxide, wherein portions of the third polycrystalline silicon layer not converted to oxide to define patterned interconnect; implanting impurities into the third polycrystalline silicon layer to form source/drain and channel regions in the third layer patterned interconnect.
Claim 3
Dependent Claim
32 words
The method of claim 1, wherein the step of forming an opening through the first oxide layer further comprises exposing a portion of the second field effect transistor gate in the opening.
Claim 4
Dependent Claim
29 words
The method of claim 1, further comprising the step of: after the step of forming a layer of gate oxide, densifying the gate oxide layer with a thermal treatment.
Claim 5
Dependent Claim
40 words
The method of claim 1, wherein the step of implanting impurities into the third polycrystalline silicon layer comprises the steps of: performing an offset implant at a first dosage level; and performing a source/drain implant at a second dosage level.
Claim 6
Dependent Claim
66 words
The method of claim 1, wherein the step of forming a second layer of patterned polycrystalline silicon comprises the steps of: forming a second layer of polycrystalline silicon over the device and in the opening to make contact with the exposed source/drain region; patterning the second layer of polycrystalline silicon; and etching selected portions of the second layer of polycrystalline silicon to define an interconnect layer.
Claim 7
Dependent Claim
94 words
The method of claim 1, wherein the step of forming a second layer of patterned polycrystalline silicon comprises the steps of: forming a second layer of polycrystalline silicon over the device and in the opening to make contact with the exposed source/drain region; masking selected portions of the second layer of polycrystalline silicon to define an interconnect layer; implanting nitrogen or oxygen into remaining portions of the second layer of polycrystalline silicon; and annealing the device to convert the material in the remaining portions of the second layer of polycrystalline silicon into an insulator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-23 | 1999-04-24 | 1999-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-23 | 2003-04-24 | 2003-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-23 | 2007-04-24 | 2007-10-24 | $7700.00 | Window Closed / Lapsed |