Patent US5459435A successfully refreshed from Google Patents.
US5459435A
Expired / Lapsed
US
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Frequency synchronous circuit for obtaining original clock signal by removing noise components
Assignee: Fujitsu Ltd
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Filing: 1994-01-25
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Granted: 1995-10-17
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Expires: 2014-01-25
Abstract
Abstract A frequency synchronous circuit has a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during a sampling time which is defined by a sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit. The comparison unit, which is connected to the storage/average unit and the second counter unit, is used to compare an output signal of the storage/average unit with an output signal of the second counter unit, and the frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of the comparison unit. Therefore, an original clock signal can be obtained and output by removing noise components from a clock signal which may include the noise components.
Inventors
- 👤 Yoshitaka Taki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:45
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/181; H03L7/08; H03L7/085
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
142 words
A frequency synchronous circuit comprising: a first counter means for counting a reference signal supplied from outside said frequency synchronous circuit during a sampling time which is defined by a sampling signal; a second counter means for counting a synchronous clock signal to be output from said frequency synchronous circuit during the sampling time of said sampling signal; a storage and average means, operatively connected to said first counter means, for storing and averaging an output signal of said first counter means; and a comparison means, connected to said storage and average means and said second counter means, for comparing an output signal of said storage and average means with an output signal of said second counter means, wherein said frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of said comparison means.
Claim 2
Dependent Claim
142 words
A frequency synchronous circuit comprising: a first counter means for counting a reference signal supplied from outside said frequency synchronous circuit during a sampling time which is defined by a sampling signal; a second counter means for counting a synchronous clock signal to be output from said frequency synchronous circuit during the sampling time of said sampling signal; a storage and average means, operatively connected to said first counter means, for storing and averaging an output signal of said first counter means; and a comparison means, connected to said storage and average means and said second counter means, for comparing an output signal of said storage and average means with an output signal of said second counter means, wherein said frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of said comparison means.
Claim 3
Dependent Claim
50 words
A frequency synchronous circuit as claimed in claim 1, wherein the output signal of said first counter means is determined in accordance with a frequency of the reference signal, and the output signal of said second counter means is determined in accordance with a frequency of the synchronous clock signal.
Claim 4
Dependent Claim
139 words
A frequency synchronous circuit as claimed in claim 1, wherein said frequency synchronous circuit further comprises: a data conversion means, connected to said comparison means, for converting the output signal of said comparison means to digital data indicating a voltage level corresponding to the output signal of said comparison means; a digital/analog converter means, connected to said data conversion means, for converting the digital data output from said data conversion means into an analog voltage; a voltage controlled oscillator means, connected to said digital/analog converter means, for generating an output signal having a frequency corresponding to the analog voltage output from said D/A converter means; and a divider means, connected to said voltage controlled oscillator means and said second counter means, for dividing the output signal of said voltage controlled oscillator means and for outputting the synchronous clock signal.
Claim 5
Dependent Claim
99 words
A frequency synchronous circuit as claimed in claim 1, wherein said frequency synchronous circuit further comprises: a first subtraction means, connected to said first counter means and said storage and average means, for subtracting a specific value from the output signal of said first counter means and for supplying the subtracted result to said storage and average means; and a second subtraction means, connected to said second counter means and said storage and average means, for subtracting the specific value from the output signal of said second counter means and for supplying the subtracted result to said comparison means.
Claim 6
Dependent Claim
24 words
A frequency synchronous circuit as claimed in claim 4, wherein the specific value is determined to be a center frequency of the reference signal.
Claim 7
Dependent Claim
96 words
A frequency synchronous circuit as claimed in claim 1, wherein said frequency synchronous circuit further comprises: a fault detection means, receiving the reference signal, for detecting a fault in the reference signal; and a write operation stop control means, connected to said fault detection means and said storage and average means, for stopping a write operation of writing new data to said storage and average means, when a fault in the reference signal is detected, so that the synchronous clock signal is continuously output in accordance with the data stored in said storage and average means.
Claim 8
Dependent Claim
52 words
A frequency synchronous circuit as claimed in claim 1, wherein at least one additional reference signal is supplied to said first counter means, said first counter means including a plurality of counters, each of said counters counting a respective one of said reference signals during the sampling time of said sampling signal.
Claim 9
Dependent Claim
59 words
A frequency synchronous circuit as claimed in claim 7, wherein said frequency synchronous circuit further comprises a selector means, connected to said plurality of counters and to said storage and average means, for selecting one output signal from a plurality of output signals from said counters and for supplying the selected output signal to said storage and average means.
Claim 10
Dependent Claim
35 words
A frequency synchronous circuit as claimed in claim 7, wherein two reference signals are supplied to said first counter means, and said first counter means includes two counters corresponding respectively to the two reference signals.
Claim 11
Dependent Claim
54 words
A frequency synchronous circuit as claimed in claim 9, wherein said frequency synchronous circuit further comprises a selector means, connected to said two counters and to said storage and average means, for selecting one output signal from said two counters and for supplying the selected one output signal to said storage and average means.
Claim 12
Dependent Claim
35 words
A frequency synchronous circuit as claimed in claim 7, wherein said frequency synchronous circuit is applied to a path protection switch ring system for one of a synchronous optical network and a synchronous digital hierarchy.
Claim 13
Dependent Claim
95 words
A frequency synchronous circuit as claimed in claim 7, wherein said frequency synchronous circuit further comprises: a fault detection means, receiving the reference signals, for detecting a fault in the reference signals; and a write operation stop control means, connected to said fault detection means and to said storage and average means, for stopping a write operation for writing new data to said storage and average means, when a fault in the reference signals is detected, the synchronous clock signal being continuously output in accordance with the data stored in said storage and average means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-16 | 1999-04-17 | 1999-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-16 | 2003-04-17 | 2003-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-16 | 2007-04-17 | 2007-10-17 | $7700.00 | Window Closed / Lapsed |