Digital processing type phase locked loop oscillator

Abstract

Abstract PURPOSE:To generate output signals having a mean frequency which is almost equal to that at the time of locking phase while the fault of an input signal continues by sequentially storing the control signals generated at that time of locking phase with the input signal, sequentially cycling and reading the stored control signals when the fault has occurred in the input signal. CONSTITUTION:When the input signal is normally added to an input terminal 1, the title oscillator is constituted similarly as a conventional digital processing type phase locked loop oscillator by a digital type phase comparator 4, a computing element 5 and a digially controlled oscillator 6. When the input signal is normal, a storage control part 8 sequentially writes the given control signals in a storage part 7. When the fault occurs in the input signal, the computing element 5 stops the new occurrence of the control signal. The storage control part 8 sequentially reads the past control signals stored in the storage part 7, and supplies them to the oscillator 6. For actual reading, the stored control signals are cycled and read. Consequently, the digital control oscillator 6 can continue maintaining the output frequency equal to that before the input fault occurs.

Inventors

• 👤 Hiroshi Muto
• 👤 武藤　宏

Bibliographic Details