Digital phase locked loop oscillator

Abstract

Abstract PURPOSE:To improve the gain at synchronization and to minimize the initial frequency deviation at asynchronization by switching a frequency control step to a digital controlled oscillator in a phase locked loop depending on synchronization and asynchronization. CONSTITUTION:When a reference clock 11 is normal, an output of a digital phase comparator 14 is subject to averaging processing by a averaging circuit 21 of a phase difference data and an oscillator control data setting circuit 23 gives a control data to a digital controlled oscillator 12 depending of the processed output. If the reference clock 11 is faulty, the control data of a control circuit 15 is not revised, held by an oscillator control data setting circuit 24, a changeover switch 25 is controlled and switched by the oscillator control data setting circuit 24.

Inventors

• 👤 Masami Kihara
• 👤 雅巳 木原

Bibliographic Details