Adiabatic dynamic logic

Claim 2

An invention, comprising: an input node for receiving an input signal having first and second logical states and involving an adiabatic transition from one potential to another potential; an output node for producing an output signal having the first and second logical states and involving an adiabatic transition from one potential to another potential; a clock node for receiving a clock signal adiabatically varying between first and second potentials, the clock signal defining a charge period during which the clock signal changes from the first potential to the second potential and a discharge period when the clock signal changes from the second potential to the first potential; and means operative in response to said clock signal for discharging said output node from a rest state selectively as a function of the state of a signal carried by the input node and for thereafter recharging said output node to said rest state selectively as a substantially exclusive function of the state of a signal carried by said output node; the input signal being substantially prevented from making transitions from one potential to another potential during a predetermined portion of the clock signal.

Claim 3

An invention, comprising: an input node for receiving an input signal having first and second logical states and involving an adiabatic transition from one potential to another potential; an output node for producing an output signal having the first and second logical states and involving an adiabatic transition from one potential to another potential; a clock node for receiving a clock signal adiabatically varying between first and second potentials, the clock signal defining a charge period during which the clock signal changes from the first potential to the second potential and a discharge period when the clock signal changes from the second potential to the first potential; and means operative in response to said clock signal for selectively connecting said clock node to said output node and discharging said output node from a rest state selectively as a function of the state of the input node and for thereafter selectively connecting said clock node to said output node to recharge it to said rest state selectively as a substantially exclusive function of the state of said output node; the input signal being substantially prevented from making transitions from one potential to another potential during a predetermined portion of the clock signal.

Claim 4

An invention, comprising: an input node for receiving an input signal having first and second logical states and involving an adiabatic transition from one potential to another potential; an output node for producing an output signal having the first and second logical states and involving an adiabatic transition from one potential to another potential; a clock node for receiving a clock signal adiabatically varying between first and second potentials, the clock signal defining a charge period during which the clock signal changes from the first potential to the second potential and a discharge period when the clock signal changes from the second potential to the first potential; and means operative in response to said clock signal for selectively connecting said clock node to said output node and discharging said output node from a rest state selectively as a function of the state of the input node and for thereafter selectively connecting said clock node to said output node to recharge it to said rest state selectively as a substantially exclusive function of the state of said output node; the input signal being substantially prevented from making transitions from one potential to another potential during a predetermined portion of the clock signal.

Claim 7

The circuit of claim 3, in which the means for selectively charging and discharging, comprises: a circuit element between the input node and the output node which performs a logical function on the input signal to produce the output signal.

Claim 8

The circuit of claim 4, in which the logical function is a NOR function.

Claim 9

The circuit of claim 4, in which the logical function is a NAND function.

Claim 10

The circuit of claim 4, in which the logical function is a noninverting function.

Claim 11

The circuit of claim 4, in which the logical function is an AND function.

Claim 12

The circuit of claim 4, in which the logical function is an OR function.

Claim 13

The circuit of claim 4, in which the logical function is a compound logical function.

Claim 14

The electronic circuit of claim 3, in which the input signal, the output signal, and the clock signal have controllable rates of change between two respective states.

Claim 15

The adiabatic dynamic logic circuit of claim 3, in which the logic element comprises a controllable switch having a control terminal and first and second output terminals.

Claim 16

The adiabatic dynamic logic circuit of claim 9, in which the clocking signal is connected to at least one of the first and second output terminals of the controllable switch.

Claim 17

The adiabatic dynamic logic circuit of claim 3, in which the apparatus defines a series resistance capacitance circuit defining an RC time constant and the transitions are such that at least one of the input signal, the output signal, and the clocking signal changes from one state to another state in an amount of time at least as great as the RC time constant.

Claim 18

The adiabatic dynamic logic circuit of claim 11, in which the first and second rates of change are each such that the clocking signal changes between the first and second states in an amount of time at least as great as ten times the RC time constant.

Claim 19

An electronic circuit, comprising: N input nodes for receiving input signals having one of two possible logic states and involving transitions between the two logic states; at least one output node for producing output signals having one of the two possible logic states as a function of the states of the input signals; a clock node for receiving clock signals comprising a substantially constant voltage first state and a substantially constant voltage second state with a precharge transition from the first state to the second state at a first predetermined adiabatic voltage rate of change and an evaluation transition from the second state to the first state at a second predetermined adiabatic voltage rate of change; and a means comprising no more than N+1 controllable switches between the N input ports and the at least one output port for selectively permitting current flow between the clock node and the output node for selectively charging the output node during the precharge transition of the clock signals in response to the state of the output signals and for selectively preventing current flow between the output node and the clock node to selectively prevent discharge of the output node in response to a predetermined state of the input signal during the evaluation transition; the input signals being substantially prevented from making transitions from one state to another state during a predetermined a portion of the clock signals.

Claim 20

An electronic circuit, comprising: N input nodes for receiving input signals having one of two possible logic states and involving transitions between the two logic states; at least one output node for producing output signals having one of the two possible logic states as a function of the states of the input signals; a clock node for receiving clock signals comprising a substantially constant voltage first state and a substantially constant voltage second state with a precharge transition from the first state to the second state at a first predetermined adiabatic voltage rate of change and an evaluation transition from the second state to the first state at a second predetermined adiabatic voltage rate of change; and a means comprising no more than N+1 controllable switches between the N input ports and the at least one output port for selectively permitting current flow between the clock node and the output node for selectively charging the output node during the precharge transition of the clock signals in response to the state of the output signals and for selectively preventing current flow between the output node and the clock node to selectively prevent discharge of the output node in response to a predetermined state of the input signal during the evaluation transition; the input signals being substantially prevented from making transitions from one state to another state during a predetermined a portion of the clock signals.

Claim 21

An electronic circuit, comprising: N input nodes for receiving input signals having one of two possible logic states and involving transitions between the two logic states; at least one output node for producing output signals having one of the two possible logic states as a function of the state of the input signals; a clock node for receiving clock signals comprising a substantially constant voltage first state and a substantially constant voltage second state with a precharge transition from the first state to the second state at a first predetermined adiabatic voltage rate of change and an evaluation transition from the second state to the first state at a second predetermined adiabatic voltage rate of change; and a means comprising no more than N controllable switches and a rectifier between the N input ports and the at least one output port for selectively permitting current flow between the clock node and the output node for selectively charging the output node during the precharge transition of the clock signals in response to the state of the output signals and for selectively preventing current flow between the output node and the clock node to selectively prevent discharge of the output node in response to a predetermined state of the input signals during the evaluation transition; the input signals being substantially prevented from making transitions from one state to another state during a predetermined portion of the clock signals.

Claim 22

An electronic circuit, comprising: N input nodes for receiving input signals having one of two possible logic states and involving transitions between the two logic states; at least one output node for producing output signals having one of the two possible logic states as a function of the state of the input signals; a clock node for receiving clock signals comprising a substantially constant voltage first state and a substantially constant voltage second state with a precharge transition from the first state to the second state at a first predetermined adiabatic voltage rate of change and an evaluation transition from the second state to the first state at a second predetermined adiabatic voltage rate of change; and a means comprising no more than N controllable switches and a rectifier between the N input ports and the at least one output port for selectively permitting current flow between the clock node and the output node for selectively charging the output node during the precharge transition of the clock signals in response to the state of the output signals and for selectively preventing current flow between the output node and the clock node to selectively prevent discharge of the output node in response to a predetermined state of the input signals during the evaluation transition; the input signals being substantially prevented from making transitions from one state to another state during a predetermined portion of the clock signals.

Claim 23

An adiabatic dynamic logic circuit, comprising: a switching element having a control terminal, a first output terminal, and a second output terminal; the control terminal carrying an input signal having two possible logic states, a first logic state comprising a substantially constant level signal and a second logic state comprising a string of pulses, the input signal being constrained to change between the potential levels in an adiabatic fashion; one of the first and second output terminals carrying an output signal having the two logic states, the output signal being constrained to change between potential levels in an adiabatic fashion; and an energy source for adiabatically clocking at least one of the terminals of the switching element.

Claim 24

An adiabatic dynamic logic circuit, comprising: a switching element having a control terminal, a first output terminal, and a second output terminal; the control terminal carrying an input signal having two possible logic states, a first logic state comprising a substantially constant level signal and a second logic state comprising a string of pulses, the input signal being constrained to change between the potential levels in an adiabatic fashion; one of the first and second output terminals carrying an output signal having the two logic states, the output signal being constrained to change between potential levels in an adiabatic fashion; and an energy source for adiabatically clocking at least one of the terminals of the switching element.

Claim 25

An electronic circuit, comprising: a transistor having a control terminal, an output terminal, and a clock terminal; the control terminal of the transistor carrying an input signal having one of a plurality of potentials and the output terminal carrying an output signal having one of a plurality of potentials as a function of the potential of the input signal; the clock terminal of the transistor carrying a clock signal adiabatically varying between a first state and a second state, the input signal being prevented from changing between the two potentials during predetermined portions of the clock signal; and a rectification means connected between the output terminal and the clock terminal for selectively charging the output terminal in response to a signal on the output terminal and selectively discharging the output terminal in response to a signal on the control terminal.

Claim 26

An electronic circuit, comprising: a transistor having a control terminal, an output terminal, and a clock terminal; the control terminal of the transistor carrying an input signal having one of a plurality of potentials and the output terminal carrying an output signal having one of a plurality of potentials as a function of the potential of the input signal; the clock terminal of the transistor carrying a clock signal adiabatically varying between a first state and a second state, the input signal being prevented from changing between the two potentials during predetermined portions of the clock signal; and a rectification means connected between the output terminal and the clock terminal for selectively charging the output terminal in response to a signal on the output terminal and selectively discharging the output terminal in response to a signal on the control terminal.